HYMD525G726BS4-K Datasheet, PDF(6/18 Page) Hynix Semiconductor – 184pin Registered DDR SDRAM DIMMs based on 512Mb B ver. (TSOP)

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HYMD525G726BS4-K Datasheet, PDF (6/18 Pages) Hynix Semiconductor – 184pin Registered DDR SDRAM DIMMs based on 512Mb B ver. (TSOP)

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184pin Registered DDR SDRAM DIMMs

IDD SPECIFICATION AND CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)

2GB, 256Mb x 72 ECC Registered DIMM: HYMD525G726BS[P]4[M]

Symbol

Test Condition

IDD0

IDD1

One bank; Active - Precharge; tRC=tRC(min); tCK=tCK(min);

DQ,DM and DQS inputs changing twice per clock cycle;

address and control inputs changing once per clock cycle

One bank; Active - Read - Precharge; Burst Length=2;

tRC=tRC(min); tCK=tCK(min); address and control inputs

changing once per clock cycle

IDD2P All banks idle; Power down mode; CKE=Low, tCK=tCK(min)

IDD2F

IDD3P

IDD3N

IDD4R

IDD4W

IDD5

/CS=High, All banks idle; tCK=tCK(min); CKE= High; address

and control inputs changing once per clock cycle. VIN=VREF

for DQ, DQS and DM

One bank active; Power down mode; CKE=Low,

tCK=tCK(min)

/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;

tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS inputs

changing twice per clock cycle; Address and other control

inputs changing once per clock cycle

Burst=2; Reads; Continuous burst; One bank active; Address

and control inputs changing once per clock cycle;

tCK=tCK(min); IOUT=0mA

Burst=2; Writes; Continuous burst; One bank active; Address

and control inputs changing once per clock cycle;

tCK=tCK(min); DQ, DM and DQS inputs changing twice per

clock cycle

tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for

DDR266A & DDR266B at 133Mhz; distributed refresh

IDD6

CKE=<0.2V; External clock on; tCK

=tCK(min)

Normal

Low Power

IDD7

Four bank interleaving with BL=4 Refer to the following page

for detailed test condition

-K

3530

4070

810

1910

882

2090

4970

6050

630

540

8210

Speed

-H

3530

4070

810

1910

882

2090

4970

6050

630

540

8210

-L

3170

Unit Note

3890

810

1910

882

2090

4430

5690

630

540

6770

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Rev. 1.1 /May. 2005

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