HYMD525G726BS4-K Datasheet, PDF (1/18 Pages) Hynix Semiconductor – 184pin Registered DDR SDRAM DIMMs based on 512Mb B ver. (TSOP)

184pin Registered DDR SDRAM DIMMs based on 512Mb B ver. (TSOP)
This Hynix Registered Dual In-Line Memory Module (DIMM) series consists of 512Mb B ver. DDR SDRAMs in 400mil.
TSOP II packages on a 184pin glass-epoxy substrate. This Hynix 512Mb B ver. based Registered DIMM series provide
a high performance 8-byte interface in 5.25" width form factor of industry standard. It is suitable for easy interchange
and addition.
FEATURES
• JEDEC Standard 184-pin dual in-line memory module
(DIMM)
• Two ranks 256M x 72 organization
• Error Check Correction (ECC) Capability
• 2.5V ± 0.2V VDD and VDDQ Power supply for
DDR333 and below
• All inputs and outputs are compatible with SSTL_2
interface
• Fully differential clock operations (CK & /CK) with
100/133 MHz
• DLL aligns DQ and DQS transition with CK transition
• Programmable CAS Latency: DDR200(2 clock),
DDR266(2, 2.5 clock)
• Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
• Edge-aligned DQS with data outs and Center-aligned
DQS with data inputs
• Auto refresh and self refresh supported
• 8192refresh cycles / 64ms
• Serial Presence Detect (SPD) with EEPROM
• Built with 512Mb DDR SDRAMs in 400 mil TSOP II
packages
• Lead-free product listed for each configuration
(RoHS compliant)
ADDRESS TABLE
2GB
Organization Ranks
SDRAMs
128M x 72
2 128Mb x 4 (Stacked)
# of
DRAMs
36
# of row/bank/column Address
13(A0~A12)/2(BA0,BA1)/12(A0~A9,A11,A12)
Refresh
Method
8K / 64ms
PREFORMANCE
Part-Number Suffix
Speed Bin
CL - tRCD- tRP
Max Clock
Frequency
CL=3
CL=2.5
CL=2
-K
DDR266A
2-3-3
-
133
133
-H
DDR266B
2.5-3-3
-
133
133
-L
Unit
DDR200
-
2-2-2
CK
-
MHz
100
MHz
100
MHz
Rev. 1.1 / May. 2005
1
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.