HYMD132725B8-M Datasheet, PDF (6/17 Pages) Hynix Semiconductor – Unbuffered DDR SDRAM DIMM

CAPACITANCE (TA=25^oC, f=100MHz )
HYMD132725B(L)8-M/K/H/L
Parameter
Pin
Input Capacitance
A0 ~ A11, BA0, BA1
Input Capacitance
/RAS, /CAS, /WE
Input Capacitance
CKE0, CKE1
Input Capacitance
CS0, CS1
Input Capacitance
CK0, /CK0, CK1, /CK1, CK2, /CK2,
Input Capacitance
DM0 ~ DM8
Data Input / Output Capacitance DQ0 ~ DQ63, DQS0 ~ DQS8
Data Input / Output Capacitance CB0 ~ CB7
Note :
1. VDD=min. to max., VDDQ=2.3V to 2.7V, VODC=VDDQ/2, VOpeak-to-peak=0.2V
2. Pins not under test are tied to GND.
3. These values are guaranteed by design and are tested on a sample basis only.
OUTPUT LOAD CIRCUIT
Symbol Min
CIN1
95
CIN2
95
CIN3
65
CIN4
60
CIN5
30
CIN6
12
CIO1
12
CIO2
12
Max
110
110
80
75
45
18
18
18
Unit
pF
pF
pF
pF
pF
pF
pF
pF
Output
VTT
RT=50Ω
Zo=50Ω
CL=30pF
VREF
Rev. 0.3/May. 02
6