HYMD116645B8J-J Datasheet, PDF (6/16 Pages) Hynix Semiconductor – Unbuffered DDR SDRAM DIMM

CAPACITANCE (TA=25^oC, f=100MHz )
HYMD116645B(L)8J-J
Parameter
Pin
Input Capacitance
Input Capacitance
Input Capacitance
Input Capacitance
Input Capacitance
Input Capacitance
Data Input / Output Capacitance
A0 ~ A11, BA0, BA1
/RAS, /CAS, /WE
CKE0
CS0
CK0, /CK0, CK1, /CK1, CK2, /CK2
DM0 ~ DM7
DQ0 ~ DQ63, DQS0 ~ DQS7
Note :
1. VDD=min. to max., VDDQ=2.3V to 2.7V, VODC=VDDQ/2, VOpeak-to-peak=0.2V
2. Pins not under test are tied to GND.
3. These values are guaranteed by design and are tested on a sample basis only.
OUTPUT LOAD CIRCUIT
Symbol Min
Max
Unit
CIN1
TBD
TBD
pF
CIN2
TBD
TBD
pF
CIN3
TBD
TBD
pF
CIN4
TBD
TBD
pF
CIN5
TBD
TBD
pF
CIN6
TBD
TBD
pF
CIO1
TBD
TBD
pF
Output
VTT
RT=50Ω
Zo=50Ω
CL=30pF
VREF
Rev. 0.3/Jun. 02
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