HY64UD16322A Datasheet, PDF (6/11 Pages) Hynix Semiconductor – 2M x 16 bit Low Low Power 1T/1C Pseudo SRAM

HY64UD16322A Series
Power-Up Sequence
1. Supply power with CS2 high.
2. Maintain stable power for longer than 200µs.
Deep Power Down Entry Sequence
1. Keep CS2 low state.
Deep power down mode is maintained while CS2 is low state.
Deep Power Down Exit Sequence
1. Keep CS2 high state.
2. Maintain stable power for longer than 200µs.
STATE DIAGRAM
PPoowweerrOOnn
WWaaiitt 220000µµss
CS2=VIH
/ CS1=VIL, CS2=VIH,
/UB&/LB≠VIH
SSttaannddbbyy
MMooddee
AAccttiivvee
CS2=VIH, /CS1=VIH
or /UB,/LB=VIH
CS2=VIL
CS2=VIL
DDeeeepp PPoowweerr
DDoowwnn MMooddee
Deep Power Down
Entry Sequence
STANDBY MODE CHARACTERISTICS
Mode
Standby
Deep Power Down
Memory Cell Data
Valid
Invalid
Standby Current[µA]
100 / 70ns
2
Wait Time[µs]
0
200
Revision 1.1
6
May. 2003