HY64UD16322A Datasheet, PDF (2/11 Pages) Hynix Semiconductor – 2M x 16 bit Low Low Power 1T/1C Pseudo SRAM

HY64UD16322A Series
2M x 16 bit Low Low Power 1T/1C SRAM
DESCRIPTION
The HY64UD16322A is a 32Mbit 1T/1C SRAM
featured by high-speed operation and super low
power consumption. The HY64UD16322A adopts
one transistor memory cell and is organized as
2,097,152 words by 16bits. The HY64UD16322A
operates in the extended range of temperature and
supports a wide operating voltage range. The
HY64UD16322A also supports the deep power
down mode for a super low standby current. The
HY64UD16322A delivers the high-density low
power SRAM capability to the high-speed low power
system.
PRODUCT FAMILY
FEATURES
• CMOS Process Technology
• 2M x 16 bit Organization
• TTL compatible and Tri-state outputs
• Deep Power Down : Memory cell data hold invalid
• Standard pin configuration : 48-FBGA(6mmX8mm)
• Data mask function by /LB, /UB
• Separated I/O Power Supply : Vddq
Product No.
HY64UD16322A-DF70E
HY64UD16322A-DF70I
Voltage
[V]
2.7~3.3
2.7~3.3
Mode
1CS with /UB,/LB:tCS¹
1CS with /UB,/LB:tCS¹
Power Dissipation
(ISB1,Max) (IDPD,Max) (ICC2,Max)
100µA
2µA
25mA
100µA
2µA
25mA
Speed
tRC[ns]
70
70
Temp.
[°C]
-25~85
-40~85
Note 1. tCS - /UB,/LB=High : Chip Deselect.
PIN CONNECTION (Top View)
BLOCK DIAGRAM
/LB /OE A0 A1 A2 CS2
IO9 /UB A3 A4 /CS1 IO1
IO10 IO11 A5 A6 IO2 IO3
Vss IO12 A17 A7 IO4 Vdd
Vddq IO13 DNU A16 IO5 Vss
IO15 IO14 A14 A15 IO6 IO7
IO16 A19 A12 A13 /WE IO8
A18 A8 A9 A10 A11 A20
A0
A20
/CS1
CS2
/WE
/OE
/LB
/UB
ROW
DECODER
MEMORY ARRAY
2,048K x 16
CONTROL
LOGIC
IO1
IO8
IO9
IO16
PIN DESCRIPTION
Pin Name
/CS1
CS2
/WE
/LB
/UB
DNU
Pin Function
Chip Select
Deep Power Down
Write Enable
Lower Byte(I/O1~I/O8)
Upper Byte(I/O9~I/O16)
Do Not Use
Pin Name
/OE
IO1~IO8
IO9~IO16
A0~A20
Vdd
Vddq
Vss
Pin Function
Output Enable
Lower Data Inputs/Outputs
Upper Data Inputs/Outputs
Address Inputs
Power Supply for Internal Circuit
Power Supply for I/O
Ground
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not
assume any responsibility for use of circuits described. No patent licenses are implied.
Revision 1.1
2
May. 2003