HMT112R7BFR8A-G7 Datasheet, PDF (5/69 Pages) Hynix Semiconductor – 240pin DDR3L SDRAM Registered DIMM

Pin Descriptions
Pin Name
CK0
CK0
CK1
CK1
CKE[1:0]
RAS
CAS
WE
S[3:0]
A[9:0],A11,
A[15:13]
A10/AP
A12/BC
BA[2:0]
SCL
SDA
SA[2:0]
Par_In
Err_Out
Description
Clock Input, positive line
Clock Input, negative line
Clock Input, positive line
Clock Input, negative line
Clock Enables
Row Address Strobe
Num
ber
1
1
1
1
2
1
Column Address Strobe
1
Write Enable
1
Chip Selects
4
Address Inputs
14
Address Input/Autoprecharge 1
Address Input/Burst chop
1
SDRAM Bank Addresses
3
Serial Presence Detect (SPD)
Clock Input
1
SPD Data Input/Output
1
SPD Address Inputs
3
Parity bit for the Address and
Control bus
1
Parity error found on the
Address and Control bus
1
Pin Name
Description
ODT[1:0] On Die Termination Inputs
DQ[63:0] Data Input/Output
CB[7:0] Data check bits Input/Output
DQS[8:0] Data strobes
DQS[8:0] Data strobes, negative line
DM[8:0]/
DQS[17:9],
TDQS[17:9]
Data Masks / Data strobes,
Termination data strobes
DQS[17:9], Data strobes, negative line,
TDQS[17:9] _{Termination data strobes}
EVENT
Reserved for optional hardware
temperature sensing
TEST
Memory bus test tool (Not Con-
nected and Not Usable on DIMMs)
RESET Register and SDRAM control pin
V_DD
V_SS
V_REFDQ
V_REFCA
V_TT
V_DDSPD
Power Supply
Ground
Reference Voltage for DQ
Reference Voltage for CA
Termination Voltage
SPD Power
Num
ber
2
64
8
9
9
9
9
1
1
1
22
59
1
1
4
1
Rev. 0.1 / Nov. 2009
5