HMT112R7BFR8A-G7 Datasheet, PDF (10/69 Pages) Hynix Semiconductor – 240pin DDR3L SDRAM Registered DIMM

Registering Clock Driver Specifications
Capacitance Values
Symbol
Parameter
Input capacitance, Data inputs
C_I
Input capacitance, CK, CK, FBIN, FBIN
Input capacitance, CK, CK, FBIN, FBIN
(DDR3-1600)
C_IR
Input capacitance, RESET, MIRROR,
QCSEN
Conditions
Min Typ Max Unit
1.5 - 2.5 pF
2
-
3
pF
1.5 - 2.5 pF
V_I = V_DD or GND; V_DD = 1.5v -
-
3
pF
Input & Output Timing Requirements
Symbol
Parameter
Conditions
f_clock
f_TEST
t_SU
t_H
t_PDM
t_DIS
t_EN
Input clock frequency
Application frequency
Input clock frequency
Test frequency
Setup time
Input valid before CK/CK
Hold time
Input to remain valid after CK/CK
Propagation delay, single-
bit switching
CK/CK to output
Output disable time (1/2-
Clock prelaunch)
Yn/Yn to output float
Output enable time (1/2-
Clock prelaunch)
Output driving to Yn/Yn
DDR3-800
1066/1333
Min
Max
300
670
70
300
100
-
175
-
0.65
1.0
0.5 tCK +
tQSK1(min)
-
0.5 tCK -
tQSK1(max)
-
Unit
Mhz
Mhz
ps
ps
ns
ps
ps
Rev. 0.1 / Nov. 2009
10