GMS36 Datasheet, PDF (43/109 Pages) Hynix Semiconductor – 4-BIT SINGLE CHIP MICROCOMPUTERS

Chapter 4. FUNCTIONAL DESCRIPTION
Watch Dog Timer (WDT)
Watch dog timer is organized binary of 14 steps. The signal of f_OSC/6 cycle comes
in the first step of WDT after WDT reset. If this counter was overflowed, reset
signal automatically come out so that internal circuit is initialized.
Ø The overflow time is 6 2 ¹³/f_OSC (108.026ms at f_OSC=455KHz.)
Ø Ø 8 6 2¹³/f_OSC (108.026ms at f_OSC = 3.64MHz)
Normally, the binary counter must be reset before the overflow by using reset
instruction (WDTR), Power-on reset pulse or Low VDD detection pulse.
* It is constantly reset in STOP mode. When STOP is released, counting is
restarted.
f_OSC/6 or f_OSC/48
Reset
by instruction
Power-On Reset
Low VDD Detection
Binary counter(14 steps)
RESET (edge-trigger)
CPU reset
Fig. 4-7 Block Diagram of Watch-dog Timer
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