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HY5PS2G431MP Datasheet, PDF (4/35 Pages) Hynix Semiconductor – 2Gb DDR2 SDRAM(DDP) | |||
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1HY5PS2G431M[P]
1HY5PS2G831M[P]
1. Description
1.1 Device Features & Ordering Information
1.1.1 Key Features
⢠Dual Die Package(1Gb DDR2 * 2)
⢠VDD, VDDQ=1.8V +/- 0.1V
⢠All inputs and outputs are compatible with SSTL_18 interface
⢠Fully differential clock inputs (CK, /CK) operation
⢠Double data rate interface
⢠Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)
⢠Differential Data Strobe (DQS, DQS)
⢠Data outputs on DQS, DQS edges when read (edged DQ)
⢠Data inputs on DQS centers when write(centered DQ)
⢠On chip DLL align DQ, DQS and DQS transition with CK transition
⢠DM mask write data-in at the both rising and falling edges of the data strobe
⢠All addresses and control inputs except data, data strobes and data masks latched on the rising
edges of the clock
⢠Programmable CAS latency 3, 4 and 5 supported
⢠Programmable additive latency 0, 1, 2, 3 and 4 supported
⢠Programmable burst length 4/8 with both nibble sequential and interleave mode
⢠Internal four bank operations with single pulsed RAS
⢠Auto refresh and self refresh supported
⢠tRAS lockout supported
⢠8K refresh cycles /64ms
⢠JEDEC standard 71ball FBGA(x4/x8)
⢠Full strength driver option controlled by EMRS
⢠On Die Termination supported
⢠Off Chip Driver Impedance Adjustment supported
⢠Read Data Strobe suupported (x8 only)
⢠Self-Refresh High Temperature Entryt
Ordering Information
Part No.
Organization
Package
HY5PS2G431M[P]-X*
HY5PS2G831M[P]-X*
512Mx4
256Mx8
Lead free**
Note:
1. -X* is the speed bin, refer to the Operation Frequency table for
complete Part No.
2. Hynix Lead-free products are compliant to RoHS.
Operating Frequency
Grade tCK(ns) CL tRCD tRP Unit
-E3
5
3
3
3 Clk
-C4
3.75 4
4
4 Clk
-Y5
3
5
5
5 Clk
Rev. 0.5 / Dec 2006
4
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