HY5PS2G431MP Datasheet, PDF(14/35 Page) Hynix Semiconductor

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

HY5PS2G431MP Datasheet, PDF (14/35 Pages) Hynix Semiconductor – 2Gb DDR2 SDRAM(DDP)

◁

1HY5PS2G431M[P]

1HY5PS2G831M[P]

3.3 Output Buffer Characteristics

3.3.1 Output AC Test Conditions

Symbol

VOTR

Parameter

Output Timing Measurement Reference Level

1. The VDDQ of the device under test is referenced.

SSTL_18 Class II

0.5 * VDDQ

Units

Notes

3.3.2 Output DC Current Drive

Symbol

Parameter

SSTl_18

Units

Notes

IOH(dc) Output Minimum Source DC Current

- 13.4

1, 3, 4

IOL(dc)

Output Minimum Sink DC Current

13.4

2, 3, 4

1. VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and VDDQ -

280 mV.

2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV.

3. The dc value of VREF applied to the receiving device is set to VTT

4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device drive

current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an SSTL_18

receiver. The actual current values are derived by shifting the desired driver operating point (see Section 3.3) along a 21 ohm

load line to define a convenient driver current for measurement.

3.3.3 OCD defalut characteristics

Description

Output impedance

Output impedance step size for OCD calibra-

tion

Pull-up and pull-down mismatch

Output slew rate

Parameter

Sout

Min

1.5

Nom

Max

1.5

Unit

ohms

Notes

ohms

V/ns

1,2,3

1,4,5,6,7,8

Note

1. Absolute Specifications ( Toper; VDD = +1.8V Â±0.1V, VDDQ = +1.8V Â±0.1V)

2. Impedance measurement condition for output source dc current: VDDQ=1.7V; VOUT=1420mV; (VOUT-VDDQ)/Ioh must be

less than 23.4 ohms for values of VOUT between VDDQ and VDDQ-280mV. Impedance measurement condition for output sink

dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol must be less than 23.4 ohms for values of VOUT between 0V and 280mV.

3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage.

4. Slew rate measured from vil(ac) to vih(ac).

5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC

to AC. This is guaranteed by design and characterization.

6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process corners/variations and

represents only the DRAM uncertainty. A 0 ohm value(no calibration) can only be achieved if the OCD impedance is 18 ohms

+/- 0.75 ohms under nominal conditions.

VTT

Output Slew rate load:

25 ohms

Output

(Vout)

Reference

point

7. DRAM output slew rate specification applies to 400 , 533 and 667 MT/s speed bins.

8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in tDQSQ and

tQHS specification.

Rev. 0.5 / Dec 2006

▷