HMT451V7AFR8A Datasheet, PDF (4/69 Pages) Hynix Semiconductor – DDR3L SDRAM VLP Registered DIMM Based on 4Gb A-die

Key Parameters
MT/s
Grade
DDR3L-1066
-G7
DDR3L-1333
-H9
DDR3L-1600
-PB
DDR3L-1866
-Rd
tCK
(ns)
1.875
1.5
1.25
1.07
CAS
Latency
(tCK)
tRCD
(ns)
tRP
(ns)
tRAS
(ns)
tRC
(ns)
CL-tRCD-tRP
7
13.125 13.125 37.5 50.625
7-7-7
9
13.5
13.5
(13.125)* (13.125)*
36
49.5
(49.125)*
9-9-9
11
13.75 13.75
(13.125)* (13.125)*
35
48.75
(48.125)*
13
13.91 13.91
(13.125)* (13.125)*
34
47.91
(48.125)*
11-11-11
13-13-13
*SK hynix DRAM devices support optional downbinning to CL 11, CL9 and CL7. SPD setting is programmed to match.
Speed Grade
Grade
-G7
-H9
-PB
-RD
CL6
CL7
800
1066
800
1066
800
1066
800
1066
Address Table
CL8
1066
1066
1066
1066
Frequency [MHz]
CL9
CL10
CL11
1333
1333
1333
1333
1333
1333
1600
1600
CL12
CL13
1866
Remark
Refresh Method
Row Address
Column Address
Bank Address
Page Size
4GB(1Rx8)
8K/64ms
A0-A15
A0-A9
BA0-BA2
1KB
8GB(1Rx4)
8K/64ms
A0-A15
A0-A9, A11
BA0-BA2
1KB
8GB(2Rx8)
8K/64ms
A0-A15
A0-A9
BA0-BA2
1KB
16GB(2Rx4)
8K/64ms
A0-A15
A0-A9, A11
BA0-BA2
1KB
16GB(4Rx8)
8K/64ms
A0-A15
A0-A9
BA0-BA2
1KB
Rev. 0.1 / May. 2013
4