GM16C550 Datasheet, PDF (4/22 Pages) Hynix Semiconductor – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFOs

GM16C550
AC Characteristics T_A = 0°C to + 70°C , V_CC = 5V ± 5%
Symbol
Parameter
Min Max Units
Conditions
Receiver
t _RINT
Delay from RD, RD (RD RBR/ or
1
RD LSR) to Reset Interupt
t _SCD
Delay from RCLK to Sample Time
2
t _SINT
Delay from Stop to Set Interrupt
1
µs
µs
RCLK
Cycles
100 pF load
Note 2
Transmitter
t _HR
t _IR
t _IRS
t _SI
Delay from WR, WR (WR THR)
To Reset Interrupt
Delay from RD, RD (RD IIR)
To Reset Interrupt (THRE)
Delay from Initial INTR Reset
To Transmit Start
Delay from Initial Write to Interrupt
t _STI
Delay from Stop to Interrupt (THRE)
t _SXV
t _WXI
Delay from Start to TXRDY Active
Delay from Write to TXRDY inactive
175
ns
100 pF load
250
ns
100 pF load
Baudout
8
24
Cycles
Baudout
16
24
Note 5
Cycles
Baudout
8
8
Note 5
Cycles
Baudout
8
100 pF load
Cycles
195
ns
100 pF load
Modem Control
t _MDO
Delay from WR, WR (WR MCR) to Output
t _RIM
t _SIM
Delay to Reset Interrupt from RD, RD
(RD MSR)
Delay to Set Interrupt from MODEM Input
200
ns
100 pF load
250
ns
100 pF load
250
ns
100 pF load
Notes
1. Applicable only when ADS is tied low.
2. In the FIFO mode (FCRO=1) the trigger level interrupts, the receiver data available indication, the active RXRDY indica-tion
and the overrun error indication will be delayed 3 RCLKs. Status indicators (PE, FE, BI) will be delayed 3 RCLKs after the first
byte has been received. For subsequently received bytes these indicators will be updated immediately after RDRBR goes
inactive. Timeout interrupt is delayed 8 RCLKs.
3. Change and discharge time is determined by VOL, VOH and the external loading.
4.In FIFO mode RC=425 ns (minimum) between reads of the receiver FIFO and the status registers (interrupt identifica- tion
register or line status register).
5. This delay will be lengthened by 1 character time, minus the last stop bit time if the transmitter interrupt delay circuit is active
(See FIFO Interrupt Mode Operatione)
4