GM16C550 Datasheet, PDF (19/22 Pages) Hynix Semiconductor – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFOs

PROGRAMMABLE BAUD
GENERATOR
The UART contains a programmable Baud Generator that is
capable of taking any clock input from 2 to 2¹⁶–1. 4MHz is
the highest input clock frequency recommended when the
divisor = 1. The output frequency of the Baud Generator is 16
× the Baud [divisor # = (frequency input) ÷ (baud rate ×16)]
Two 8-bit latches store the divisor in a 16-bit binary format.
These Divisor Latches must be loaded during initialization to
ensure proper operation of the Baud Generator. Upon loading
either or the Divisor Latches, a 16-bit Baud counter is
immediately loaded.
Tables III, IV and V provide decimal divisors to use with
crystal frequencies of 1.8432 MHz 3.072MHz and 8 MHz,
respectively. For baud rates of 38400 and below, the error
obtain is minimal. The accuracy of the desired baud rate is
dependent on the crystal frequency chosen. Using a divisor of
zero is not recommended.
LINE STATUS REGISTER
This register provides status information to the CPU
concerning the data transfer. Table II shows the contents of
the Line Status Register. Details on each bit follow.
Bit 0: This bit is the receiver Data Ready (DR) indicator. Bit
0 is set to logic 1whenever a complete incoming character has
been received and transferred into the Receiver Buffer
Register or the FIFO. Bit 1 is reset to a logic 0 by reading all
of the data in the Receiver Buffer Register or the FIFO.
Bit 1: This bit is the Overrun Error (OE) indicator. Bit 1
indicates that data in the Receiver Buffer Register was not
read by the CPU before the next character was transferred
into the Receiver Buffer Register, thereby destroying the
previous character. The OE indicator is set to a logic 1 upon
detection of an overrun condition and reset whenever the
CPU reads the contents of the Line Status Register
If the FIFO mode data continues to fill the FIFO beyond the
trigger level, An overrun error will occur only been
completely received in the shift register. OE is indicated to
the CPU as soon as it happens. The character on the shift
register is overwritten, but is not transferred to the FIFO.
Bit 2: This bit is the Parity Error (PE) indicator. Bit 2
indicates that the received data character does not have the
correct even or odd parity. As selected by the even –parity-
select bit. The PE bit is set to a logic 1 upon detection of a
parity error and is reset to a logic 0 whenever the CPU reads
the contents of the Line Status Register. In the FIFO mode
this error is associated with the particular character in the
when its associated character is at the top of the FIFO.
Bit 3: This bit is the Framing Error (FE) indicator.
Bit3 indicates that the received character did not have a valid
Stop bit. Bit 3is set to logic 1 whenever the Stop bit following
the last data bit or parity bit is detected as a logic 0 bit
(Spacing level). The FE indicator is reset whenever the CPU
reads the contents of the Line Status Register. In the FIFO
mode this error is associated with the particular character in
the FIFO it applies to. This error is revealed to the CPU when
GM16C550
its associated character is at the top of the FIFO. The UART
will try to resynchronize after a framing error. To do this it
assumes that the framing error was due to the next start bit so
it samples this “start” bit twice and then takes in the “data”.
Bit 4: This bit is the Break Interrupt (BI) indicator.
Bit 4 is set to a logic 1 when ever the received data input is
held in the spacing (logic) state for longer than a full word
transmission time (that is, the total time of Start Bit + data
bits + Parity + Stop bits). The BI indicator is reset whenever
the CPU reads the contents of the line Status Register. In the
FIFO mode this error is associated with the particular
character in the FIFO it applies to. This error is revealed to
the CPU when its associated character is at the top of the
FIFO. When break occurs only one zero character is loaded
into the FIFO. The next character transfer is enabled after
SIN goes to the marking state and receives the next valid start
bit.
Note: Bits 1 through 4 are the error conditions that produce a
Receiver Line Status interrupt whenever any of the
corresponding conditions are detected and the interrupt is
enabled.
Bit 5: This bit is the Transmitter Holding Register Empty
(THRE) indicator. Bit 5 indicates that the UART is ready to
accept a new character for transmission. In addition, this bit
causes the UART to issue an interrupt to the CPU when the
Transmit Holding Register Empty Interrupt enable is set high.
The THRE bit is set to logic 1 when a character is transferred
from the Transmitter Holding Register into the Transmitter
Shift Register. The bit is reset to logic 0 concurrently with the
loading of the Transmitter Holding Register by the CPU, In
the FIFO mode this bit is set when the XMIT FIFO is empty;
it is cleared when at least 1 byte is written to the XMIT FIFO.
Bit 6: This bit is the Transmitter Empty (TEMT) indicator.
Bit 6 is set to a logic 1 whenever the Transmitter Holding
Register (THR) and the Trans-mitter shift register (TSR) are
both empty. It is reset to a logic 0 whenever either the THR or
TSR contains a data character. In the FIFO mode this bit is set
to one whenever the transmitter FIFO and shift register are
both empty.
Bit 7: in the GM16C450 Mode this is a 0. In the FIFO mode
LSR7 is set when there is least one parity error, framing error
or break indication in the FIFO. LSR7 is cleared when the
CPU reads the LSR, if there are no subsequent errors in the
FIFO.
Note: The Line Status Register is intended for read op-
erations only. Writing to this register is not recom-mended as
this operation is only used for factory testing.
FIFO CONTROL REGISTER
This is a write only register at the same location as the IIR
(the IIR is a read only register). This register is used to enable
the FIFOs, set the RCVR FIFO trigger level, and select the
type of DMA signaling.
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