H5PS1G63EFR-20L Datasheet, PDF (33/80 Pages) Hynix Semiconductor – 1Gb(64Mx16) DDR2 SDRAM

Seamless Burst Write Operation: RL = 5, WL = 4, BL = 4
H5PS1G63EFR
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK/CK
CMD ^{Post CAS}
Write A
DQS/
DQS
DQ’s
NOP
Post CAS
Write B
WL = RL - 1 = 4
NOP
NOP
DQS
DQS
NOP
NOP
NOP
NOP
DIN A₀ DIN A₁ DIN A₂ DIN A₃ DIN B0 DIN B₁ DIN B₂ DIN B₃
The seamless burst write operation is supported by enabling a write command every other clock for BL = 4
operation, every four clocks for BL = 8 operation. This operation is allowed regardless of same or different
banks as long as the banks are activated
Rev. 1.1/ Oct. 2008
33