H5PS1G63EFR-20L Datasheet, PDF (14/80 Pages) Hynix Semiconductor – 1Gb(64Mx16) DDR2 SDRAM

H5PS1G63EFR
EMR(2)
The extended mode register(2) controls refresh related features. The default value of the extended mode reg-
ister(2) is not defined, therefore the extended mode register(2) must be programmed during initialization for
proper operation. The extended mode register(2) is written by asserting LOW on /CS,/RAS,/CAS,/WE, HIGH
on BA1 and LOW on BA0, while controling the states of address pins A0~A15. The DDR2 SDRAM should be
in all bank precharge with CKE already HIGH prior to writing into the extended mode register(2). The mode
register set command cycle time(tMRD) must be satisfied to complete the write operation to the extended
mode register(2). Mode register contents can be changed using the same command and clock cycle require-
ments during normal operation as long as all banks are in the precharge state.
EMR(2) Programming:
BA2 BA1 BA0 A15 ~ A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ^{Address Field}
0*¹ 1 0
BA1
0
0
1
1
BA0
0
1
0
1
0*¹
SRF
0*¹
DCC*3
A7
High Temp Self-refresh Rate Enable
0
Disable
1
Enable(Optional)*²
MR mode
MR
EMR(1)
EMR(2)
EMR(3):Reserved
A3 DCC Enable(Optional)*4
0
Disable
1
Enable
PASR*3
Extended Mode
Register(2)
A2
A1
A0
Partial Array Self Refresh for 8 banks Partial Array Self Refresh for 4 banks
0
0
0
Full Array
Full Array
0
0
1
Half Array (BA[2:0]=000,001,010&011)
Half Array (BA[1:0]=00&01)
0
1
0
Quarter Array (BA[2:0]=000&001)
Quarter Array (BA[1:0]=00)
0
1
1
1/8th Array (BA[2:0]=000)
Not Defined
1
0
0
3/4 Array (BA[2:0]=010,011,100,101,110&111)
3/4 Array (BA[1:0]=01,10&11)
1
0
1
Half Array (BA[2:0]=100,101,110&111)
Half Array (BA[1:0]=10&11)
1
1
0
Quarter Array (BA[2:0]=110&111)
Quarter Array (BA[1:0]=11)
1
1
1
1/8th Array (BA[2:0]=111)
Not Defined
*1 : The rest bits in EMR(2) are reserved for future use and all bits except A7, BA0 and BA1 must be programmed to 0 when setting the
mode register during initialization.
*2 : Currently the periodic Self-Refresh interval is hard coded whithin the DRAM to a specific value. EMR(2) bit A7 is a migration plan to
support higher Self-Refresh entry. However, since this Self-Refresh control function is an option and to be phased-in by manufacturer
individually, checking on the DRAM parts for function availablity is necessary. For more details, please refer to “Operating Temperature
Condition” section at “Chapter 5. AC & DC operation conditions”.
*3 Optional in DDR2 SDRAM. If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified
address range will be lost if self refresh is entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh com-
mand is issued. If the PASR feature is not supported, EMR(2)[A0-A2] must be set to 000 when programming EMR(2).
*4 Optional in DDR2 SDRAM. JEDEC standard DDR2 SDRAM may or may not have DCC (Duty Cycle Corrector) implemented, and in
some of the DRAMs implementing DCC, user may be given the controllability of DCC thru EMR(2)[A3] bit. JEDEC standard DDR2
SDRAM users can look at manufacturer's data sheet to check if the DRAM part supports DCC controllability. If Optional DCC Controlla-
bility is supported, user may enable or disable the DCC by programming EMR(2)[A3] accordingly. If the controllability feature is not sup-
ported, EMR(2)[A3] must be set to 0 when programming EMR(2).
Rev. 1.1/ Oct. 2008
14