HY5DU56422CT-D4 Datasheet, PDF (30/34 Pages) Hynix Semiconductor – 256M-P DDR SDRAM

Parameter
Input Pulse Width
Write DQS High Level Width
Write DQS Low Level Width
Clock to First Rising edge of DQS-In
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Data-In Setup Time to DQS-In (DQ & DM)
Data-in Hold Time to DQS-In (DQ & DM)
DQ & DM Input Pulse Width
Read DQS Preamble Time
Read DQS Postamble Time
Write DQS Preamble Setup Time
Write DQS Preamble Hold Time
Write DQS Postamble Time
Mode Register Set Delay
Exit self refresh to non-READ command
Exit self refresh to READ command
Exit Self Refresh to Any Execute Command
Average Periodic Refresh Interval
HY5DU56422CT-D4/D43
HY5DU56822CT-D4/D43
HY5DU561622CT-D4/D43
Symbol
tIPW
tDQSH
tDQSL
tDQSS
tDSS
tDSH
tDS
tDH
tDIPW
tRPRE
tRPST
tWPRES
tWPREH
tWPST
tMRD
tXSNR
tXSRD
tXSC
tREFI
DDR400 (D4)
Min
Max
2.2
-
0.35
-
0.35
-
0.72
1.28
0.2
0.2
0.4
-
0.4
-
1.6
-
0.9
1.1
0.4
0.6
0
-
0.25
-
0.4
0.6
2
-
75
-
200
-
200
-
-
7.8
DDR400 (D43)
Min
Max
2.2
-
0.35
-
0.35
-
0.72
1.28
0.2
0.2
0.4
-
0.4
-
1.6
-
0.9
1.1
0.4
0.6
0
-
0.25
-
0.4
0.6
2
-
75
-
200
-
200
-
-
7.8
Unit Note
ns
6
CK
CK
CK
CK
CK
ns _6,7,11,
ns ^12,13
ns
6
CK
CK
CK
CK
CK
CK
ns
CK
8
CK
8
us
Rev. 0.3 / Oct. 2003
30