HY5DU56422CT-D4 Datasheet, PDF (24/34 Pages) Hynix Semiconductor – 256M-P DDR SDRAM

HY5DU56422CT-D4/D43
HY5DU56822CT-D4/D43
HY5DU561622CT-D4/D43
DC CHARACTERISTICS II (TA=0 to 70 ^oC, Voltage referenced to VSS = 0V)
32Mx8
Parameter Symbol
Test Condition
Operating Current
Operating Current
Precharge Power
Down Standby
Current
Idle Standby Current
Active Power Down
Standby Current
Active Standby
Current
Operating Current
Operating Current
Auto Refresh Current
Self Refresh Current
Operating Current -
Four Bank Operation
IDD0
One bank; Active - Precharge;
tRC=tRC(min); tCK=tCK(min); DQ,DM and
DQS inputs changing twice per clock cycle;
address and control inputs changing once
per clock cycle
IDD1
One bank; Active - Read - Precharge;
Burst=2; tRC=tRC(min); tCK=tCK(min);
address and control inputs changing once
per clock cycle; IOUT=0mA
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
IDD2F
/CS=High, All banks idle; tCK=tCK(min);
CKE=High; address and control inputs
changing once per clock cycle.
VIN=VREF for DQ, DQS and DM
IDD3P
One bank active; Power down mode ;
CKE=Low, tCK=tCK(min)
IDD3N
/CS=HIGH; CKE=HIGH; One bank; Active-
Precharge; tRC=tRAS(max); tCK=tCK(min);
DQ, DM and DQS inputs changing twice per
clock cycle; Address and other control inputs
changing once per clock cycle
IDD4R
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing
once per clock cycle; tCK=tCK(min);
IOUT=0mA
IDD4W
Burst=2; Writes; Continuous burst; One
bank active; Address and control inputs
changing once per clock cycle;
tCK=tCK(min); DQ, DM and DQS inputs
changing twice per clock cycle
IDD5 tRC=tRFC(min); All banks active
IDD6
CKE=<0.2V; External clock on; ^Normal
tCK=tCK(min)
Low Power
IDD7
Four bank interleaving with BL=4, Refer to
the following page for detailed test condition
Speed
Unit Note
-D4 -D43
115
120
mA
125
130
mA
10
mA
55
mA
15
mA
65
mA
210
mA
265
mA
180
mA
3
mA
1.5
mA
300
mA
Rev. 0.3 / Oct. 2003
24