English
Language : 

HY5DS573222F Datasheet, PDF (3/28 Pages) Hynix Semiconductor – 256M(8Mx32) GDDR SDRAM
1HY5DS573222F(P)
DESCRIPTION
The Hynix HY5DS573222 is a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the
point-to-point applications which requires high bandwidth.
The Hynix 8Mx32 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
• The Hynix HY5DS573222F(P) guarantee until
166MHz speed at DLL_off condition
• 1.8V VDD and VDDQ wide range max power supply
supports
• All inputs and outputs are compatible with SSTL_2
interface
• 12mm x 12mm, 144ball FBGA with 0.8mm pin pitch
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous - data transaction aligned to
bidirectional data strobe (DQS0 ~ DQS3)
• Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
• Data(DQ) and Write masks(DM) latched on the both
rising and falling edges of the data strobe
• All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
• Write mask byte controls by DM (DM0 ~ DM3)
• Programmable /CAS Latency 5 / 4 supported
• Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
• Internal 4 bank operations with single pulsed /RAS
• tRAS Lock-Out function supported
• Auto refresh and self refresh supported
• 4096 refresh cycles / 32ms
• Half strength and Matched Impedance driver option
ORDERING INFORMATION
Part No.
HY5DS573222F(P)-28
HY5DS573222F(P)-33
HY5DS573222F(P)-36
HY5DS573222F(P)-4
Power Supply
VDD/VDDQ 1.8V
Clock
Frequency
350MHz
300MHz
275MHz
250MHz
Max Data Rate
700Mbps/pin
600Mbps/pin
550Mbps/pin
500Mbps/pin
interface
SSTL_2
Package
12mm x 12mm
144Ball FBGA
Note) Hynix supports Lead free parts for each speed grade with same specification, except Lead free materials.
We'll add "P" character after "F" for lead free product.
For example, the part number of 300Mhz Lead free product is HY5DS573222FP-33.
Rev. 1.0 / Feb. 2005
3