HY5DS573222F Datasheet, PDF (22/28 Pages) Hynix Semiconductor – 256M(8Mx32) GDDR SDRAM

1HY5DS573222F(P)
DC CHARACTERISTICS II (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Test Condition
Speed
28
33
36
Unit Note
4
Operating Current
One bank; Active - Precharge;
tRC=tRC(min); tCK=tCK(min); DQ,DM
IDD0 and DQS inputs changing twice per
190 170 160 140 mA 1
clock cycle; address and control inputs
changing once per clock cycle
Operating Current
IDD1
Burst length=2, One bank active
tRC ≥ tRC(min), IOL=0mA
210 200 180 170 mA 1
Precharge Standby Current
in Power Down Mode
IDD2P CKE ≤ VIL(max), tCK=min
25 25 25 25 mA
Precharge Standby Current
in Non Power Down Mode
IDD2N
CKE ≥ VIH(min), /CS ≥ VIH(min), tCK =
min, Input signals are changed one
time during 2clks
130
120
110
100
mA
Active Standby Current in
Power Down Mode
IDD3P CKE ≤ VIL(max), tCK=min
25 25 25 25 mA
Active Standby Current in
Non Power Down Mode
CKE ≥ VIH(min), /CS ≥ VIH(min),
IDD3N tCK=min, Input signals are changed one 160 150 130 120 mA
time during 2clks
Burst Mode Operating Cur-
rent
IDD4
tCK ≥ tCK(min), IOL=0mA
All banks active
650 550 500 500 mA 1
Auto Refresh Current
IDD5
tRC ≥ tRFC(min),
All banks active
300 300 300 270 mA 1,2
Self Refresh Current
IDD6 ^{CKE ≤ 0.2V}
6
6
6
6
mA
Operating Current - Four
Bank Operation
Four bank interleaving with BL=4, Refer
IDD7 to the following page for detailed test 600 550 500 500 mA
condition
Note :
1. IDD1, IDD4 and IDD5 depend on output loading and cycle rates. Specified values are measured with the output open.
2. Min. of tRFC (Auto Refresh Row Cycle Time) is shown at AC CHARACTERISTICS.
Rev. 1.0 / Feb. 2005
22