HY5DU323222Q Datasheet, PDF (26/29 Pages) Hynix Semiconductor – 32M(1Mx32) DDR SDRAM

1HY5DU323222Q
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
Row Cycle Time
Auto Refresh Row Cycle Time
Row Active Time
Row Address to Column Address Delay for
Read
Row Address to Column Address Delay for
Write
Row Active to Row Active Delay
Column Address to Column Address Delay
Row Precharge Time
Last Data-In to Precharge Delay Time
(Write Recovery Time : tWR)
Last Data-In to Read Command
Auto Precharge Write Recovery +
Precharge Time
System Clock Cycle Time
CL = 3.0
Clock High Level Width
Clock Low Level Width
Data-Out edge to Clock edge Skew
DQS-Out edge to Clock edge Skew
DQS-Out edge to Data-Out edge Skew
Data-Out hold time from DQS
Clock Half Period
Data Hold Skew Factor
Input Setup Time
Input Hold Time
Write DQS High Level Width
Write DQS Low Level Width
Clock to First Rising edge of DQS-In
Symbol
tRC
tRFC
tRAS
tRCDRD
tRCDWR
tRRD
tCCD
tRP
tDPL
tDRL
tDAL
tCK
tCH
tCL
tAC
tDQSCK
tDQSQ
tQH
tHP
tQHS
tIS
tIH
tDQSH
tDQSL
tDQSS
5
Min
Max
60
-
70
-
40
120K
4
-
2
2
1
4
2
2
6
5
0.45
0.45
-0.9
-0.7
-
tHPmin
-tQHS
tCH/L
min
-
1.0
1.0
0.4
0.4
0.75
-
-
-
-
-
-
-
10
0.55
0.55
0.9
0.7
0.4
-
-
0.75
-
-
0.6
0.6
1.25
6
Min
Max
66
-
72
-
45
120K
4
-
3
2
1
4
2
2
6
6
0.45
0.45
-0.9
-0.7
-
tHPmin
-tQHS
tCH/L
min
-
1.0
1.0
0.4
0.4
0.75
-
-
-
-
-
-
-
10
0.55
0.55
0.9
0.7
0.4
-
-
0.75
-
-
0.6
0.6
1.25
Unit Note
ns
ns
ns
CK
CK
CK
CK
CK
CK
CK
CK
ns
CK
CK
CK
ns
ns
ns
1,6
ns
1,5
ns
6
ns
2
ns
2
ns
CK
CK
Rev. 0.5 / Jun. 2005
26