HY5DU56422BT-D4 Datasheet, PDF (25/32 Pages) Hynix Semiconductor – 256M-P DDR SDRAM

HY5DU56422BT-D4/D43
HY5DU56822BT-D4/D43
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7
IDD1 : Operating current: One bank operation
1. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are
changing once per clock cycle. lout = 0mA
2. Timing patterns
- DDR400(200Mhz, CL=3) : tCK = 5ns, CL=3, BL=4, tRCD = 3*tCK, tRC = 11*tCK, tRAS = 8*tCK
Read : A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing
50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
IDD7 : Operating current: Four bank operation
1. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not
changing. lout = 0mA
2. Timing patterns
- DDR400(200Mhz, CL=3) : tCK = 5ns, CL=3, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge
Read : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 - repeat the same timing with random address changing
50% of data changing at every burst
Legend : A=Activate, R=Read, RA=Read with Auto Precharge, W=Write, P=Precharge, N=NOP
Rev. 0.4 / Aug. 2003
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