HY5DW283222AF Datasheet, PDF (24/28 Pages) Hynix Semiconductor – 128M(4Mx32) GDDR SDRAM

HY5DW283222AF
AC CHARACTERISTICS - I (AC operating conditions unless otherwise noted)
Parameter
22
Symbol
Min Max
25
Min Max
28
Min Max
33
Min Max
4
Min Max
Unit Note
Row Cycle Time
tRC
21
-
18
-
17
-
15
-
13
- CK
Auto Refresh Row Cycle Time
tRFC
24
-
21
-
19
-
17
-
15
- CK
Row Active Time
tRAS
14 120K 12 120K 10 120K 9 120K
8
120K CK
Row Address to Column
Address Delay for Read
tRCDRD 7
-
6
-
6
-
6
-
5
- CK
Row Address to Column
Address Delay for Write
tRCDWR 3
-
3
-
2
-
2
-
2
- CK
Row Active to Row Active Delay tRRD
4
-
4
-
4
-
3
-
3
- CK
Column Address to Column
Address Delay
tCCD
2
-
1
-
1
-
1
-
1
- CK
Row Precharge Time
tRP
7
-
6
-
6
-
6
-
5
- CK
Write Recovery Time
tWR
4
-
3
-
3
-
3
-
3
- CK
Last Data-In to Read Command tDRL
2
-
2
-
2
-
2
-
2
- CK
Auto Precharge Write Recovery
+ Precharge Time
tDAL
11
-
9
-
9
-
9
-
8
- CK
System Clock
Cycle Time
CL=5
CL=4
2.2
6
2.5
6
2.8
6
-
-
-
-
ns
tCK
-
-
-
-
-
-
3.3
6
4
10 ns
Clock High Level Width
tCH
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 CK
Clock Low Level Width
tCL
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 CK
Data-Out edge to Clock edge
Skew
tAC
-0.45 0.45 -0.6
0.6
-0.6 0.6 -0.6 0.6
-0.6
0.6
ns
DQS-Out edge to Clock edge
Skew
tDQSCK -0.45 0.45 -0.6 0.6 -0.6 0.6 -0.6 0.6 -0.6
0.6 ns
DQS-Out edge to Data-Out
edge Skew
tDQSQ
-
0.35
-
0.35
-
0.35
-
0.35
-
0.4 ns
Data-Out hold time from DQS
tQH
tHPmin
-tQHS
-
tHPmin
-tQHS
-
tHPmin
-tQHS
-
tHPmin
-tQHS
-
tHPmin
-tQHS
-
ns 1,6
Clock Half Period
tHP
tCH/L
min
-
tCH/L
min
-
tCH/L
min
-
tCH/L
min
-
tCH/L
min
-
ns 1,5
Data Hold Skew Factor
tQHS
-
0.35
-
0.35
-
0.35
-
0.35
-
0.4 ns 6
Input Setup Time
tIS
0.75
-
0.75
-
0.75
-
0.75
-
0.75
-
ns 2
Input Hold Time
tIH
0.75
-
0.75
-
0.75
-
0.75
-
0.75
-
ns 2
Write DQS High Level Width
tDQSH 0.4 0.6 0.4
0.6
0.4 0.6 0.4 0.6
0.4
0.6 CK
Write DQS Low Level Width
tDQSL 0.4 0.6 0.4
0.6
0.4 0.6 0.4 0.6
0.4
0.6 CK
Rev. 0.5 / Jun. 2004
24