HY5DW283222AF Datasheet, PDF (22/28 Pages) Hynix Semiconductor – 128M(4Mx32) GDDR SDRAM

DC CHARACTERISTICS II (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
HY5DW283222AF
Parameter Symbol
Test Condition
22
25
One bank; Active -
Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and
Operating Current
IDD0
DQS inputs changing twice
per clock cycle; address
210
190
and control inputs
changing once per clock
cycle
Burst length=4, One bank
Operating Current IDD1 active tRC ≥ tRC(min),
230 210
IOL=0mA
Precharge
Standby Current
in Power Down
IDD2P CKE ≤ VIL(max), tCK=min
40
35
Mode
Precharge
CKE ≥ VIH(min), /CS ≥
Standby Current
in Non Power
IDD2N
VIH(min), tCK = min,
Input signals are changed
130
120
Down Mode
one time during 2clks
Active Standby
Current in Power IDD3P CKE ≤ VIL(max), tCK=min
50
45
Down Mode
Active Standby
Current in Non
Power Down
Mode
CKE ≥ VIH(min), /CS ≥
IDD3N
VIH(min), tCK=min, Input
signals are changed one
190
170
time during 2clks
Burst Mode Oper-
ating Current
IDD4
tCK ≥ tCK(min), IOL=0mA
All banks active
700 650
Auto Refresh Cur-
rent
IDD5
tRC ≥ tRFC(min),
All banks active
400 350
Self Refresh Cur-
rent
IDD6 ^{CKE ≤ 0.2V}
3
3
Operating Current
- Four Bank
Operation
IDD7
Four bank interleaving
with BL=4, Refer to the
following page for detailed
test condition
1000
900
Speed
28
33
180
170
200
190
30
25
80
70
35
30
130
115
490
420
350
300
3
3
800
700
Unit Note
4
160
mA 1
180
mA 1
25
mA
60
mA
30
mA
100
mA
350
mA 1
300
mA 1,2
3
mA
600
mA
Note :
1. IDD1, IDD4 and IDD5 depend on output loading and cycle rates. Specified values are measured with the output open.
2. Min. of tRFC (Auto Refresh Row Cycle Time) is shown at AC CHARACTERISTICS.
Rev. 0.5 / Jun. 2004
22