HY5DU561622CTP Datasheet, PDF (24/30 Pages) Hynix Semiconductor – 256M(16Mx16) gDDR SDRAM

1HY5DU561622CTP
AC CHARACTERISTICS - I (AC operating conditions unless otherwise noted)
Parameter
Symbol
Row Cycle Time
(Manual Precharge)
tRC
Row Cycle Time
(Auto Precharge)
tRC_APCG
Auto Refresh Row Cycle Time
tRFC
Row Active Time
tRAS
Row Address to Column Address Delay
tRCDRD
tRCDWT
Row Active to Row Active Delay
tRRD
Column Address to Column Address Delay tCCD
Row Precharge Time
tRP
Last Data-In to Precharge Delay
(Write Recovery Time : tWR)
tDPL
Last Data-In to Read Command
tDRL
Auto Precharge Write Recovery +
Precharge Time
tDAL
System Clock Cycle Time
CL = 4.0
tCK
CL = 3.0
Clock High Level Width
tCH
Clock Low Level Width
tCL
Data-Out edge to Clock edge Skew
tAC
DQS-Out edge to Clock edge Skew
tDQSCK
DQS-Out edge to Data-Out edge Skew tDQSQ
Data-Out hold time from DQS
tQH
Clock Half Period
tHP
Data Hold Skew Factor
tQHS
Input Setup Time
tIS
Input Hold Time
tIH
Write DQS High Level Width
tDQSH
Write DQS Low Level Width
tDQSL
Clock to First Rising edge of DQS-In
tDQSS
Data-In Setup Time to DQS-In (DQ & DM) tDS
28
Min Max
20
-
33
Min Max
18
-
36
Min Max
Unit Note
16
-
CK
21
-
19
-
18
-
24
-
22
-
20
-
40
70K
40
70K
40
70K
6
-
6
-
5
-
2
-
2
-
2
-
2
-
2
-
2
-
1
-
1
-
1
-
6
-
6
-
5
-
4
-
3
-
3
-
2
-
2
-
2
-
10
-
9
-
8
-
2.8
7.0
3.3
7.0
3.6
7.0
-
-
-
-
-
-
0.45 0.55 0.45 0.55 0.45 0.55
0.45 0.55 0.45 0.55 0.45 0.55
-0.7
0.7
-0.7
0.7
-0.7
0.7
-0.7
0.7
-0.7
0.7
-0.7
0.7
-
0.4
-
0.4
-
0.4
tHPmin
-tQHS
-
tHPmin
-tQHS
-
tHPmin
-tQHS
-
tCH/L
min
-
tCH/L
min
-
tCH/L
min
-
-
0.4
-
0.4
-
0.4
0.75
-
0.75
-
0.75
-
0.75
-
0.75
-
0.75
-
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.85 1.15 0.85 1.15 0.85 1.15
0.4
-
0.4
-
0.4
-
CK
CK
ns
CK
CK
CK
CK
CK
CK
CK
CK
ns
ns
CK
CK
ns
ns
ns
ns 1, 6
ns 1, 5
ns
6
ns
2
ns
2
CK
CK
CK
ns
3
Rev. 0.5 / Feb. 2006
24