HY5DU283222F Datasheet, PDF (24/30 Pages) Hynix Semiconductor – 128M(4Mx32) GDDR SDRAM

HY5DU283222F
AC CHARACTERISTICS - I (AC operating conditions unless otherwise noted)
Parameter
Symbol
26
Min
Max
Row Cycle Time
tRC
59.8
-
Auto Refresh Row Cycle Time
tRFC
65
-
Row Active Time
tRAS
41.6
120K
Row Address to Column Address Delay for Read tRCDRD
7
-
Row Address to Column Address Delay for Write tRCDWR
4
-
Row Active to Row Active Delay
tRRD
2
-
Column Address to Column Address Delay
tCCD
1
-
Row Precharge Time
tRP
7
-
Write Recovery Time
tWR
3
-
Last Data-In to Read Command
tDRL
2
-
Auto Precharge Write Recovery + Precharge Time tDAL
10
-
System Clock Cycle Time
CL=4
CL=3
2.6
6
tCK
-
-
Clock High Level Width
tCH
0.45
0.55
Clock Low Level Width
tCL
0.45
0.55
Data-Out edge to Clock edge Skew
tAC
-0.9
0.9
DQS-Out edge to Clock edge Skew
tDQSCK
-0.7
0.7
DQS-Out edge to Data-Out edge Skew
tDQSQ
-
0.4
Data-Out hold time from DQS
tQH
tHPmin
-tQHS
-
Clock Half Period
tHP
tCH/L
min
-
Data Hold Skew Factor
tQHS
-
0.5
Input Setup Time
tIS
0.75
-
Input Hold Time
tIH
0.75
-
Write DQS High Level Width
tDQSH
0.4
0.6
Write DQS Low Level Width
tDQSL
0.4
0.6
Clock to First Rising edge of DQS-In
tDQSS
0.75
1.25
Data-In Setup Time to DQS-In (DQ & DM)
tDS
0.4
-
Data-In Hold Time to DQS-In (DQ & DM)
tDH
0.4
-
Read DQS Preamble Time
tRPRE
0.7
1.1
28
Min
Max
61.6
-
64.4
-
42
120K
7
-
4
-
2
-
1
-
7
-
3
-
2
-
10
-
2.8
6
-
-
0.45
0.55
0.45
0.55
-0.9
0.9
-0.7
0.7
-
0.4
tHPmin
-tQHS
-
tCH/L
min
-
-
0.5
0.75
-
0.75
-
0.4
0.6
0.4
0.6
0.75
1.25
0.4
-
0.4
-
0.7
1.1
33
Min
Max
Unit Note
62.7
-
ns
66
-
ns
42.9
120K ns
6
-
CK
3
-
CK
2
-
CK
1
-
CK
6
-
CK
3
-
CK
2
-
CK
9
-
CK
3.3
6
ns
-
-
ns
0.45
0.55 CK
0.45
0.55 CK
-0.9
0.9
ns
-0.7
0.7
ns
-
0.4
ns
tHPmin
-tQHS
-
ns 1,6
tCH/L
min
-
ns 1,5
-
0.5
ns 6
0.75
-
ns 2
0.75
-
ns 2
0.4
0.6 CK
0.4
0.6 CK
0.75
1.25 CK
0.4
-
ns 3
0.4
-
ns 3
0.7
1.1 CK
Rev. 1.2/Sep. 02
24