HY5DS283222BF Datasheet, PDF (24/28 Pages) Hynix Semiconductor – 128M(4Mx32) GDDR SDRAM

1HY5DS283222BF(P)
AC CHARACTERISTICS - I (AC operating conditions unless otherwise noted)
Parameter
Symbol
28
Min Max
33
Min Max
36
Min Max
4
Min Max
Unit Note
Row Cycle Time
tRC
17
-
15
-
14
-
13
-
CK
Auto Refresh Row Cycle Time
tRFC
19
-
17
-
16
-
15
-
CK
Row Active Time
tRAS
10
100K
9
100K
9
100K
8
100K CK
Row Address to Column Address
Delay for Read
tRCDRD
6
-
6
-
5
-
5
-
CK
Row Address to Column Address
Delay for Write
tRCDWR
4
-
3
-
2
-
2
-
CK
Row Active to Row Active Delay
tRRD
4
-
3
-
3
-
3
-
CK
Column Address to Column Address
Delay
tCCD
1
-
1
-
1
-
1
-
CK
Row Precharge Time
tRP
6
-
6
-
5
-
5
-
CK
Write Recovery Time
tWR
4
-
3
-
3
-
3
-
CK
Last Data-In to Read Command
tDRL
2
-
2
-
2
-
2
-
CK
Auto Precharge Write Recovery +
Precharge Time
tDAL
10
-
9
-
8
-
8
-
CK
CL=5
System Clock Cycle Time
tCK
CL=4
2.8
10
3.3
10
3.6
10
4
10 ns
-
-
-
-
-
-
4
10
Clock High Level Width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55 CK
Clock Low Level Width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55 CK
Data-Out edge to Clock edge Skew
tAC
-0.6
0.6
-0.6
0.6
-0.6
0.6
-0.6
0.6 ns
DQS-Out edge to Clock edge Skew
tDQSCK
-0.6
0.6
-0.6
0.6
-0.6
0.6
-0.6
0.6 ns
DQS-Out edge to Data-Out edge
Skew
tDQSQ
-
0.35
-
0.35
-
0.4
-
0.4 ns
Data-Out hold time from DQS
tQH
tHPmin
-tQHS
-
tHPmin
-tQHS
-
tHPmin
-tQHS
-
tHPmin
-tQHS
-
ns 1,6
Clock Half Period
tHP
tCH/L
min
-
tCH/L
min
-
tCH/L
min
-
tCH/L
min
-
ns 1,5
Data Hold Skew Factor
tQHS
-
0.35
-
0.35
-
0.4
-
0.4 ns 6
Input Setup Time
tIS
0.75
-
0.75
-
0.75
-
0.75
-
ns 2
Input Hold Time
tIH
0.75
-
0.75
-
0.75
-
0.75
-
ns 2
Write DQS High Level Width
tDQSH
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6 CK
Write DQS Low Level Width
tDQSL
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6 CK
Clock to First Rising edge of DQS-In tDQSS
0.85
1.15
0.85
1.15
0.85
1.15
0.85
1.15 CK
Rev. 1.0 / Feb. 2005
24