HMP112P7EFR8C-C4_1 Datasheet, PDF (24/32 Pages) Hynix Semiconductor – 240pin Registered DDR2 SDRAM DIMMs

1240pin Registered DDR2 SDRAM DIMMs
(DDR2-667 & DDR2-800)
Parameter
Symbol
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
tAC
tDQSCK
tCH
tCL
CK half period
tHP
Clock cycle time, CL=x
DQ and DM input setup time
(differential strobe)
DQ and DM input hold time
(differential strobe)
Control & Address input pulse width for each input
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
DQ/DQS output hold time from DQS
First DQS latching transition to associated clock
edge
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write preamble
Write postamble
Auto-Refresh to Active/Auto-Refresh command
period
Row Active to Row Active Delay
for 1KB page size
Address and control input setup time
Address and control input hold time
Read preamble
Read postamble
Activate to precharge command
Active to active command period for 1KB page size
products
Row Active to Row Active Delay
for 2KB page size
Four Active Window for 1KB page size products
Four Activate Window for 2KB page size
CAS to CAS command delay
Write recovery time
Auto precharge write recovery + precharge time
Internal write to read command delay
Internal read to precharge command delay
tCK
tDS
tDH
tIPW
tDIPW
tHZ
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tQH
tDQSS
tDQSH
tDQSL
tDSS
tDSH
tMRD
tWPRE
tWPST
tRFC
tRRD
tIS
tIH
tRPRE
tRPST
tRAS
tRRD
tRRD
tFAW
tFAW
tCCD
tWR
tDAL
tWTR
tRTP
DDR2-667
min
max
-450
+450
-400
+400
0.45
0.55
0.45
0.55
min(tCL,
-
tCH)
3000
8000
100
-
175
0.6
0.35
-
tAC min
2*tAC min
-
-
tHP - tQHS
- 0.25
0.35
0.35
0.2
0.2
2
0.35
0.4
127.5
7.5
200
275
0.9
0.4
45
7.5
10
37.5
50
2
15
WR+tRP
7.5
7.5
-
-
-
tAC max
tAC max
tAC max
240
340
-
+ 0.25
-
-
-
-
-
-
0.6
-
-
-
-
1.1
0.6
70000
-
-
-
-
-
-
-
DDR2-800
min
max
-400
+400
-350
+350
0.45
0.55
0.45
0.55
min(tCL,
-
tCH)
2500
50
-
Unit Note
ps
ps
tCK
tCK
ps
ps
ps
1
125
-
ps
1
0.6
0.35
-
tAC min
2*tAC min
-
-
tHP - tQHS
-
tCK
-
tCK
tAC max
ps
tAC max
ps
tAC max
ps
200
ps
300
ps
-
ps
- 0.25
+ 0.25
tCK
0.35
0.35
0.2
0.2
2
0.35
0.4
-
tCK
-
tCK
-
tCK
-
tCK
-
tCK
-
tCK
0.6
tCK
127.5
-
ns
7.5
-
ns
175
-
ps
250
-
ps
0.9
1.1
tCK
0.4
0.6
tCK
45
70000
ns
7.5
-
ns
10
-
ns
35
50
2
15
WR+tRP
7.5
7.5
-
ns
-
ns
tCK
-
ns
-
tCK
-
ns
ns
Rev. 0.3 / Oct. 2008
24