HB7121BELECTRONICS Datasheet, PDF (24/29 Pages) Hynix Semiconductor – CMOS IMAGE SENSOR With 8-bit ADC

Electronics Industries Co., Ltd.
System IC Division
PRELIMINARY
HB7121B
CMOS IMAGE SENSOR
With 8-bit ADC
MCLK
HSYNC
VSYNC
.....
DATA
G
R
B
GB
.......
Time _≈
Slot
IMAGE RAW DATA
Window Width
804 clocks
Line Tail
Blank
12 clocks
HBLANK
3 clocks
VSYNC
3 clocks
Line Head
Blank
12 clocks
IMAGE RAW DATA
Window Width
≈
804 clocks
Integration Time < EffectiveWindowHeight * Scale
Fig.4 Frame Transition Timing
(2) Frame Timing Diagram for Integration Time > (EffectiveWindowHeight * Scale)
Frame timing related registers are programmed to suit for the above condition as follows
RowStartAddress = 6;
WindowHeight = 302;
ColumnStartAddress = 6;
WindowWidth = 402;
IntegrationTime = 600 [Line Mode];
EffectiveWindowHeight is “302” for (SensorArrayHeight > (RowStartAddress + WindowHeight + 1)),
i.e. 314 > (6 + 302 + 1), is met, and Scale is “1” for integration time is line mode. Therefore,
(Integration Time < EffectiveWindowHeight * Scale), i.e. 600 > 302 * 1, is met, and Idle Slot of Line
Mode, i.e. (600 - 302) * 1024 clocks idle slot, is inserted before the next frame initiation.
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume
any responsibility for use of circuits described. NO patent licenses are implied.
DA21991011R_1.0
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1999 Hyundai System IC Division