HB7121BELECTRONICS Datasheet, PDF (21/29 Pages) Hynix Semiconductor – CMOS IMAGE SENSOR With 8-bit ADC

Electronics Industries Co., Ltd.
System IC Division
PRELIMINARY
HB7121B
CMOS IMAGE SENSOR
With 8-bit ADC
When Integration Time > (EffectiveWindowHeight * Scale), next frame VSYNC does not follow immediately
after current frame’ s last line has been produced. Instead, one of the following two idle time slots is inserted
according to Integration Time Mode before next frame VSYNC gets active.
< Idle Slots >
l Line Mode: (Integration Time - EffectiveWindowHeight) * 1024 clocks
l Pixel Mode: (Integration Time - EffectiveWindowHeigth * Scale)
= (Integration Time - EffectiveWindowHeigth * SensorArrayWidth) clocks
Each Frame Timing of the above cases may be decomposed into four timing segments
l Initial Data Setup Time after ENB gets active
l Even Line
l Odd Line
l Frame Transition
The subsections will describe frame timing diagram for said frame time cases, (Integration Time < Effective Window
Height * Scale) and (Integration Time > Effective Window Height * Scale)
(1) Frame Timing Diagram for Integration Time < (EffectiveWindowHeight * Scale)
Frame timing related registers are programmed to suit for the above condition as follows
RowStartAddress = 6;
WindowHeight = 302;
ColumnStartAddress = 6;
WindowWidth = 402;
IntegrationTime = 200 [Line Mode];
EffectiveWindowHeight is “302” for (SensorArrayHeight > (RowStartAddress + WindowHeight + 1)), i.e. 314 >
(6 + 302 + 1), is met, and Scale is “1” for integration time is line mode.
Therefore, (Integration Time< EffectiveWindowHeight * Scale), i.e. 200 < 302 * 1, is met.
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume
any responsibility for use of circuits described. NO patent licenses are implied.
DA21991011R_1.0
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1999 Hyundai System IC Division