HMT112R7TFR8A-G7 Datasheet, PDF (22/69 Pages) Hynix Semiconductor – 240pin DDR3L SDRAM Registered DIMM

4GB, 512Mx72 Module(4Rank of x8) - page3
S0
S1
1:2
S2
S3
R
BA[N:0]
E
G
A[N:0]
I
RAS
S
T
CAS
E
WE
R
/
CKE0
P
L
CKE1
L
ODT0
ODT1
CK0
CK0
CK1
120Ω
CK1
± 5%
PAR_IN
RESET RST
CS0 → CS0: SDRAMs U[10:2]
CS1 → CS1: SDRAMs U[19:11]
CS2 → CS2: SDRAMs U[28:20]
CS3 → CS3: SDRAMs U[37:29]
WBA[N:0] → BA[N:0]: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29]
EBA[N:0] → BA[N:0]: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34]
WA[N:0] → A[N:0]: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29]
EA[N:0] → A[N:0]: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34]
WRAS → RAS: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29]
ERAS → RAS: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34]
WCAS → CAS: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29]
ECAS → CAS: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34]
WWE → WE: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29]
EWE → WE: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34]
WCKE0 → CKE0: SDRAMs U[6:2], U[24:20]
ECKE0 → CKE0: SDRAMs U[10:7], U[28:25]
WCKE1 → CKE1: SDRAMs U[15:11], U[33:29]
ECKE1 → CKE1: SDRAMs U[19:16], U[37:34]
WODT0 → ODT0: SDRAMs U[6:2]
EODT0 → ODT0: SDRAMs U[10:7]
WODT0 → ODT1: SDRAMs U[24:20]
EODT0 → ODT1: SDRAMs U[28:25]
PCK0 → CK: SDRAMs U[6:2], U[15:11]
PCK1 → CK: SDRAMs U[10:7], U[28:25]
PCK2 → CK: SDRAMs U[24:20], U[33:29]
PCK3 → CK: SDRAMs U[19:16], U[37:34]
PCK0 → CK: SDRAMs U[6:2], U[15:11]
PCK1 → CK: SDRAMs U[10:7], U[28:25]
PCK2 → CK: SDRAMs U[24:20], U[33:29]
PCK3 → CK: SDRAMs U[19:16], U[37:34]
Err_Out
RST: SDRAMs U[37:2]
Rev. 0.1 / Dec. 2009
22