HMS77C1000A Datasheet, PDF (20/45 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

HMS77C1000A/HMS77C1001A
8. ARCHITECTURE
8.1 CPU Architecture
The HMS700 core is a RISC-based CPU and uses a modi-
fied Harvard architecture. This architecture uses two sepa-
rate memories with separate address buses, one for the
program memory and the other for the data memory. This
architecture adapts 33 single word instructions that are 12-
bit wide instruction and has an internal 2-stage pipeline
(fetch and execute), which results in execution of one in-
struction per single cycle(200ns @ 20MHz) except for pro-
gram branches.
The HMS77C100XA can address 1K x 12 Bits program
memory and 25 Bytes data memory. And it can directly or
indirectly address data memory.
The HMS700 core has three special function registers -
PC, STATUS and FSR - in data memory map and has ATU
(Address Translation Unit) to provide address for data
memory and has an 8-bit general purpose ALU and work-
ing register(W) as an accumulator. The W register consists
of 8-bit register and it can not be an addressed register.
Instruction
Immediate Data
Instruction
Decode
&
Control
Unit
Control
Signals
Program Memory Address
PC with 2-level Stack
STATUS
FSR
Indirect Address
Address Translation
Unit
ALU
Status
W
ALU
FIGURE 8-1 HMS700 CPU BLOCK DIAGRAM
Data Bus
Data Memory Bus
Oct. 2001 Ver. 2.0
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