HYMD564M646A6-J Datasheet, PDF (2/17 Pages) Hynix Semiconductor – Unbuffered DDR SO-DIMM

DESCRIPTION
64Mx64 bits
Unbuffered DDR SO-DIMM
HYMD564M646A(L)6-J/K/H
Preliminary
Hynix HYMD564M646A(L)6-J/K/H series is unbuffered 200-pin double data rate Synchronous DRAM Small Outline
Dual In-Line Memory Modules (SO-DIMMs) which are organized as 64Mx64 high-speed memory arrays. Hynix
HYMD564M646A(L)6-J/K/H series consists of eight 32Mx16 DDR SDRAM in 400mil TSOP II packages on a 200pin
glass-epoxy substrate. Hynix HYMD564M646A(L)6-J/K/H series provide a high performance 8-byte interface in
67.60mmX 31.75mm form factor of industry standard. It is suitable for easy interchange and addition.
Hynix HYMD564M646A(L)6-J/K/H series is designed for high speed of up to 166MHz and offers fully synchronous
operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs
are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both ris-
ing and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth.
All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and
burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD564M646A(L)6-J/K/H series incorporates SPD(serial presence detect). Serial presence detect function is
implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify
DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
• 512MB (64M x 64) Unbuffered DDR SO-DIMM
based on 32Mx16 DDR SDRAM
• JEDEC Standard 200-pin small outline dual in-line
memory module (SO-DIMM)
• 2.5V +/- 0.2V VDD and VDDQ Power supply
both rising and falling edges of the clock
• Data inputs on DQS centers when write (centered
DQ)
• Data strobes synchronized with output data for read
and input data for write
• All inputs and outputs are compatible with SSTL_2 • Programmable CAS Latency 2 / 2.5 supported
interface
• Programmable Burst Length 2 / 4 / 8 with both
• Fully differential clock operations (CK & /CK) with
sequential and interleave mode
133MHz/166MHz
• tRAS Lock-out function supported
•
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
•
Internal four bank operations with single pulsed RAS
of the clock
• Auto refresh and self refresh supported
• Data(DQ), Data strobes and Write masks latched on _{• 8192 refresh cycles / 64ms}
ORDERING INFORMATION
Part No.
HYMD564M646A(L)6-J
HYMD564M646A(L)6-K
HYMD564M646A(L)6-H
Power Supply
VDD=2.5V
VDDQ=2.5V
Clock Frequency
166MHz (*DDR333)
133MHz (*DDR266A)
133MHz (*DDR266B)
Interface
Form Pactor
SSTL_2
200pin Unbuffered SO-DIMM
67.6mm x 31.75mm x 1mm
* JEDEC Defined Specifications compliant
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.4 / Oct. 2004
2