HY29DS322 Datasheet, PDF (2/6 Pages) Hynix Semiconductor – 32 Megabit (4M x 8/2M x16) Super-Low Voltage, Dual Bank, Simultaneous Read/Write, Flash Memory

HY29DS322/HY29DS323
GENERAL DESCRIPTION
The HY29DS322/HY29DS323 (HY29DS32x) is a
32 Mbit, 2.0 volt-only CMOS Flash memory orga-
nized as 4,194,304 (4M) bytes or 2,097,152 (2M)
words. The device is available in 48-pin TSOP
and 48-ball FBGA packages. Word-wide data
(x16) appears on DQ[15:0] and byte-wide (x8) data
appears on DQ[7:0].
The HY29DS32x Flash memory array is organized
into 71 sectors in two banks. Bank 1 contains
eight 8 KByte boot/parameter sectors and 7 or 15
larger sectors of 64 KBytes each, depending on
the version of the device. Bank 2 contains the
rest of the memory array, organized as 56 or 48
sectors of 64 KBytes:
Bank 1
Bank 2
HY29DS322
8 x 8KB/4KW
7 x 64KB/32KW
56 x 64KB/32KW
HY29DS323
8 x 8KB/4KW
15 x 64KB/32KW
48 x 64KB/32KW
The device features simultaneous read/write op-
eration, which allows the host system to invoke a
program or erase operation in one bank and im-
mediately and simultaneously read data from the
other bank, except if that bank has any sectors
marked for erasure, with zero latency. This re-
leases the system from waiting for the completion
of program or erase operations, thus improving
overall system performance.
The HY29DS32x can be programmed and erased
in-system with a single 2.0 volt ± 10% V_CC supply.
Internally generated and regulated voltages are
provided for program and erase operations, so that
the device does not require a higher voltage V_PP
power supply to perform those functions. The de-
vice can also be programmed in standard EPROM
programmers. Access times as low as 100ns are
offered for timing compatibility with the zero wait
state requirements of high speed microproces-
sors. To eliminate bus contention, the HY29DS32x
has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
The device is compatible with the JEDEC single-
power-supply Flash command set standard. Com-
mands are written to the command register using
standard microprocessor write timings, from where
they are routed to an internal state-machine that
controls the erase and programming circuits.
Device programming is performed a byte/word at
a time by executing the four-cycle Program Com-
mand write sequence. This initiates an internal
algorithm that automatically times the program
pulse widths and verifies proper cell margin. Faster
programming times can be achieved by placing
the HY29DS32x in the Unlock Bypass mode, which
requires only two write cycles to program data in-
stead of four.
The HY29DS32x’s sector erase architecture al-
lows any number of array sectors, in one or both
banks, to be erased and reprogrammed without
affecting the data contents of other sectors. De-
vice erasure is initiated by executing the Erase
Command sequence. This initiates an internal al-
gorithm that automatically preprograms the sec-
tor before executing the erase operation. As dur-
ing programming cycles, the device automatically
times the erase pulse widths and verifies proper
cell margin. Hardware Sector Group Protection
optionally disables both program and erase op-
erations in any combination of the sector groups,
while Temporary Sector Group Unprotect, which
requires a high voltage on one pin, allows in-sys-
tem erasure and code changes in previously pro-
tected sector groups. Erase Suspend enables the
user to put erase on hold in a bank for any period
of time to read data from or program data to any
sector in that bank that is not selected for era-
sure. True background erase can thus be
achieved. Because the HY29DS32x features si-
multaneous read/write capability, there is no need
to suspend to read from a sector located within a
bank that does not contain sectors marked for era-
sure. The device is fully erased when shipped
from the factory.
Addresses and data needed for the programming
and erase operations are internally latched during
write cycles. The host system can detect comple-
tion of a program or erase operation by observing
the RY/BY# pin or by reading the DQ[7] (Data#
Polling) and DQ[6] (Toggle) status bits. Hardware
data protection measures include a low V_CC de-
tector that automatically inhibits write operations
during power transitions.
After a program or erase cycle has been com-
pleted, or after assertion of the RESET# pin (which
terminates any operation in progress), the device
is ready to read data or to accept another com
2
PB May 01