HYMD116725B8-M Datasheet, PDF (16/17 Pages) Hynix Semiconductor – Unbuffered DDR SDRAM DIMM

HYMD116725B(L)8-M/K/H/L
SERIAL PRESENCE DETECT
Bin Sort : M(DDR266(2-2-2),K(DDR266A@CL=2),
H(DDR266B@CL=2.5),L(DDR200@CL=2)
Byte#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36~40
41
42
43
44
45
46~61
62
63
Function Description
Number of Bytes written into serial memory at module
manufacturer
Total number of Bytes in SPD device
Fundamental memory type
Number of row address on this assembly
Number of column address on this assembly
Number of physical banks on DIMM
Module data width
Module data width (continued)
Module voltage Interface levels(VDDQ)
DDR SDRAM cycle time at CAS Latency =2.5(tCK)
DDR SDRAM access time from clock at CL=2.5 (tAC)
Module configuration type
Refresh rate and type
Primary DDR SDRAM width
Error checking DDR SDRAM data width
Minimum clock delay for back-to-back random column
address(tCCD)
Burst lengths supported
Number of banks on each DDR SDRAM
CAS latency supported
CS latency
WE latency
DDR SDRAM module attributes
DDR SDRAM device attributes : General
DDR SDRAM cycle time at CL=2.0(tCK)
DDR SDRAM access time from clock at CL=2.0(tAC)
DDR SDRAM cycle time at CL=1.5(tCK)
DDR SDRAM access time from clock at CL=1.5(tAC)
Minimum row precharge time(tRP)
Minimum row activate to row active delay(tRRD)
Minimum RAS to CAS delay(tRCD)
Minimum active to precharge time(tRAS)
Module row density
Command and address signal input setup time(tIS)
Command and address signal input hold time(tIH)
Data signal input setup time(tDS)
Data signal input hold time(tDH)
Reserved for VCSDRAM
Minimum active / auto-refresh Time (tRC)
Minimum auto-refresh to active / auto-refresh com-
mand period(tRFC)
Maximum cycle time (tCK max)
Maximum DQS-DQ skew time (tDQSQ)
Maximum read data hold skew factor (tQHS)
Superset Information(may be used in future)
SPD Revision code
Checksum for Bytes 0~62
Function Supported
M
K
H
L
128 Bytes
7.5ns
256 Bytes
DDR SDRAM
12
10
1Bank
72 Bits
-
SSTL 2.5V
7.5ns 7.5ns
8.0ns
+/-0.75ns
+/-0.8ns
ECC
15.6us & Self refresh
x8
x8
1 CLK
2,4,8
4 Banks
2, 2.5
0
1
Differential Clock Input
+/-0.2Voltage tolerance,
Concurrent Auto Precharge
tRAS Lock Out
7.5ns 7.5ns 10ns
10ns
+/-0.75ns
+/-0.8ns
-
-
15ns 20ns 20ns
20ns
15ns 15ns 15ns
15ns
15ns 20ns 20ns
20ns
45ns 45ns 45ns
50ns
128MB
0.9ns 0.9ns 0.9ns
1.1ns
0.9ns 0.9ns 0.9ns
1.1ns
0.5ns 0.5ns 0.5ns
0.6ns
0.5ns 0.5ns 0.5ns
0.6ns
Undefined
60ns 65ns 65ns
70ns
75ns 75ns 75ns
80ns
12ns
0.5ns
0.75ns
12ns 12ns
0.5ns 0.5ns
0.75ns 0.75ns
Undefined
Initial release
-
12ns
0.6ns
0.75ns
Hexa Value
Note
M
K
H
L
80h
08h
07h
0Ch
1
0Ah
1
01h
48h
00h
04h
75h 75h 75h 80h 2
75h 75h 75h 80h 2
02h
80h
08h
08h
01h
0Eh
04h
0Ch
01h
02h
20h
C0h
75h 75h A0h A0h
75h 75h 75h 80h
00h
00h
3Ch 50h 50h 50h
3Ch 3Ch 3Ch 3Ch
3Ch 50h 50h 50h
2Dh 2Dh 2Dh 32h
20h
90h 90h 90h B0h
90h 90h 90h B0h
50h 50h 50h 60h
50h 50h 50h 60h
00h
3Ch 41h 41h 46h
4Bh 4Bh 4Bh 50h
30h 30h 30h 30h
32h 32h 32h 3Ch
75h 75h 75h 75h
00h
00h
79h A6h D1h 6Bh
Rev. 0.3/May. 02
16