HYMD264G726BLF8-J Datasheet, PDF (15/16 Pages) Hynix Semiconductor – Registered DDR SDRAM DIMM

SERIAL PRESENCE DETECT
Byte#
Function Description
0
Number of Bytes written into serial memory at module
manufacturer
1 Total number of Bytes in SPD device
2 Fundamental memory type
3 Number of row address on this assembly
4 Number of column address on this assembly
5 Number of physical banks on DIMM
6 Module data width
7 Module data width (continued)
8 Module voltage Interface levels(VDDQ)
9 DDR SDRAM cycle time at CAS Latency=2.5(tCK)
10 DDR SDRAM access time from clock at CL=2.5 (tAC)
11 Module configuration type
12 Refresh rate and type
13 Primary DDR SDRAM width
14 Error checking DDR SDRAM data width
15
Minimum clock delay for back-to-back random column
address(tCCD)
16 Burst lengths supported
17 Number of banks on each DDR SDRAM
18 CAS latency supported
19 CS latency
20 WE latency
21 DDR SDRAM module attributes
22 DDR SDRAM device attributes : General
23
24
25
26
27
28
29
30
31
32
33
34
35
36~40
41
42
43
44
45
46~61
62
63
DDR SDRAM cycle time at CL=2.0(tCK)
DDR SDRAM access time from clock at CL=2.0(tAC)
DDR SDRAM cycle time at CL=1.5(tCK)
DDR SDRAM access time from clock at CL=1.5(tAC)
Minimum row precharge time(tRP)
Minimum row activate to row active delay(tRRD)
Minimum RAS to CAS delay(tRCD)
Minimum active to precharge time(tRAS)
Module row density
Command and address signal input setup time(tIS)
Command and address signal input hold time(tIH)
Data signal input setup time(tDS)
Data signal input hold time(tDH)
Reserved for VCSDRAM
Minimum active / auto-refresh time ( tRC)
Minimum auto-refresh to active/auto-refresh
command period(tRFC)
Maximum cycle time (tCK max)
Maximim DQS-DQ skew time(tDQSQ)
Maximum read data hold skew factor(tQHS)
Superset information(may be used in future)
SPD Revision code
Checksum for Bytes 0~62
HYMD264G726B(L)F8-J
Function Supported
128 Bytes
256 Bytes
DDR SDRAM
13
10
2Bank
72 Bits
-
SSTL 2.5V
6.0ns
+/-0.7ns
ECC
7.8us & Self refresh
x8
x8
1 CLK
2,4,8
4 Banks
2, 2.5
0
1
Registered, PLL
+/-0.2Voltage tolerance,
Concurrent Auto Precharge
tRAS Lock Out
7.5ns
+/-0.7ns
-
-
18ns
12ns
18ns
42ns
256MB
0.75ns
0.75ns
0.45ns
0.45ns
Undefined
60ns
72ns
12ns
0.4ns
0.5ns
Undefined
Initial release
-
Bin Sort :J(DDR333)
Hexa Value
Note
80h
08h
07h
0Dh
1
0Ah
1
02h
48h
00h
04h
60h
2
70h
2
02h
82h
08h
08h
01h
0Eh
04h
0Ch
01h
02h
26h
C0h
75h
2
70h
2
00h
2
00h
2
48h
30h
48h
2Ah
40h
75h
75h
45h
45h
00h
3Ch
48h
30h
40h
50h
00h
00h
27h
Rev. 0.1 / Mar. 2003
15