HYMD264G726BLF4N-D43 Datasheet, PDF (15/16 Pages) Hynix Semiconductor – Registered DDR SDRAM DIMM

SERIAL PRESENCE DETECT
Byte#
Function Description
0
Number of Bytes written into serial memory at module
manufacturer
1 Total number of Bytes in SPD device
2 Fundamental memory type
3 Number of row address on this assembly
4 Number of column address on this assembly
5 Number of physical banks on DIMM
6 Module data width
7 Module data width (continued)
8 Module voltage Interface levels(VDDQ)
9 DDR SDRAM cycle time at CAS Latency=2.5(tCK)
10 DDR SDRAM access time from clock at CL=2.5 (tAC)
11 Module configuration type
12 Refresh rate and type
13 Primary DDR SDRAM width
14 Error checking DDR SDRAM data width
15
Minimum clock delay for back-to-back random column
address(tCCD)
16 Burst lengths supported
17 Number of banks on each DDR SDRAM
18 CAS latency supported
19 CS latency
20 WE latency
21 DDR SDRAM module attributes
22 DDR SDRAM device attributes : General
23 DDR SDRAM cycle time at CL=2.0(tCK)
24 DDR SDRAM access time from clock at CL=2.0(tAC)
25 DDR SDRAM cycle time at CL=1.5(tCK), 2.0(tCK)
26 DDR SDRAM access time from clock at CL=1.5(tAC)
27 Minimum row precharge time(tRP)
28 Minimum row activate to row active delay(tRRD)
29 Minimum RAS to CAS delay(tRCD)
30 Minimum active to precharge time(tRAS)
31 Module row density
32 Command and address signal input setup time(tIS)
33 Command and address signal input hold time(tIH)
34 Data signal input setup time(tDS)
35 Data signal input hold time(tDH)
36~40 Reserved for VCSDRAM
41 Minimum active / auto-refresh time ( tRC)
42
Minimum auto-refresh to active/auto-refresh
command period(tRFC)
43 Maximum cycle time (tCK max)
44 Maximim DQS-DQ skew time(tDQSQ)
45 Maximum read data hold skew factor(tQHS)
46~61 Superset information(may be used in future)
62 SPD Revision code
63 Checksum for Bytes 0~62
HYMD264G726B(L)F4N-D43
Function Supported
128 Bytes
256 Bytes
DDR SDRAM
13
11
1Bank
72 Bits
-
SSTL 2.5V
5.0ns
+/-0.7ns
ECC
7.8us & Self refresh
x4
x4
1 CLK
2,4,8
4 Banks
2, 2.5, 3
0
1
Registered, PLL
+/-0.2Voltage tolerance,
Concurrent Auto Precharge
tRAS Lock Out
6.0ns
+/-0.7ns
7.5ns
+/-0.75ns
15ns
10ns
15ns
40ns
512MB
0.60ns
0.60ns
0.40ns
0.40ns
Undefined
55ns
70ns
10ns
0.4ns
0.5ns
Undefined
Initial release
-
Bin Sort :D43(DDR400@CL3)
Hexa Value
80h
08h
07h
0Dh
0Bh
01h
48h
00h
50h
50h
70h
02h
82h
04h
04h
01h
0Eh
04h
1Ch
01h
02h
26h
Note
1
1
2
2
C0h
60h
2
70h
2
75h
2
75h
2
3Ch
28h
3Ch
28h
80h
60h
60h
40h
40h
00h
37h
46h
28h
40h
50h
00h
00h
B7h
Rev. 0.1 / Sep. 2003
15