HYMD264G726BLF4N-D43 Datasheet, PDF (1/16 Pages) Hynix Semiconductor – Registered DDR SDRAM DIMM

DESCRIPTION
64Mx72 bits
Registered DDR SDRAM DIMM
HYMD264G726B(L)F4N-D43
Preliminary
Hynix HYMD264G726B(L)F4N-D43 series is registered 184-pin double data rate Synchronous DRAM Dual In-Line
Memory Modules (DIMMs) which are organized as 64Mx72 high-speed memory arrays.
Hynix HYMD264G726B(L)F4N-D43 series consists of eighteen 64Mx4 DDR SDRAM in FBGA packages on a 184pin
glass-epoxy substrate. Hynix HYMD264G726B(L)F4N-D43 series provide a high performance 8-byte interface in 5.25"
width form factor of industry standard. It is suitable for easy interchange and addition.
Hynix HYMD264G726B(L)F4N-D43 series is designed for high speed of up to 200MHz and offers fully synchronous
operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs
are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both ris-
ing and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth.
All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and
burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD264G726B(L)F4N-D43 series incorporates SPD(serial presence detect). Serial presence detect function
is implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to iden-
tify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
• 512MB (64M x 72) Registered DDR DIMM based on • Fully differential clock operations (CK & /CK) with
64Mx4 DDR SDRAM
166MHz/200MHz
• JEDEC Standard 184-pin dual in-line memory mod-
ule (DIMM)
• Programmable CAS Latency 3 for DDR400,
2.5 for DDR333 supported
• Error Check Correction (ECC) Capability
• Programmable Burst Length 2 / 4 / 8 with both
• Registered inputs with one-clock delay
sequential and interleave mode
• tRAS Lock-out function supported
• Phase-lock loop (PLL) clock driver to reduce loading
• 2.6V +/- 0.1V VDD and VDDQ Power supply
• Internal four bank operations with single pulsed RAS
• All inputs and outputs are compatible with SSTL_2
• Auto refresh and self refresh supported
interface
• 8192 refresh cycles / 64ms
ORDERING INFORMATION
Part No.
HYMD264G726B(L)F4N-D43
Power Supply
VDD=2.6V
VDDQ=2.6V
Clock Frequency
200MHz (*DDR400)
Interface
Form Factor
SSTL_2
184pin Registered DIMM
5.25 x 1.125 x 0.15 inch
* JEDEC Defined Specifications compliant
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.1 / Sep. 2003
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