HYMD132725B8J-J Datasheet, PDF (15/16 Pages) Hynix Semiconductor – Unbuffered DDR SDRAM DIMM

SERIAL PRESENCE DETECT
Byte#
Function Description
0 Number of Bytes written into serial memory at module manufacturer
1 Total number of Bytes in SPD device
2 Fundamental memory type
3 Number of row address on this assembly
4 Number of column address on this assembly
5 Number of physical banks on DIMM
6 Module data width
7 Module data width (continued)
8 Module voltage Interface levels(VDDQ)
9 DDR SDRAM cycle time at CAS Latency=2.5(tCK)
10 DDR SDRAM access time from clock at CL=2.5 (tAC)
11 Module configuration type
12 Refresh rate and type
13 Primary DDR SDRAM width
14 Error checking DDR SDRAM data width
15
Minimum clock delay for back-to-back random column
address(tCCD)
16 Burst lengths supported
17 Number of banks on each DDR SDRAM
18 CAS latency supported
19 CS latency
20 WE latency
21 DDR SDRAM module attributes
22 DDR SDRAM device attributes : General
23 DDR SDRAM cycle time at CL=2.0(tCK)
24 DDR SDRAM access time from clock at CL=2.0(tAC)
25 DDR SDRAM cycle time at CL=1.5(tCK)
26 DDR SDRAM access time from clock at CL=1.5(tAC)
27 Minimum row precharge time(tRP)
28 Minimum row activate to row active delay(tRRD)
29 Minimum RAS to CAS delay(tRCD)
30 Minimum active to precharge time(tRAS)
31 Module row density
32 Command and address signal input setup time(tIS)
33 Command and address signal input hold time(tIH)
34 Data signal input setup time(tDS)
35 Data signal input hold time(tDH)
36~40 Reserved for VCSDRAM
41 Minimum active / auto-refresh Time (tRC)
42
Minimum auto-refresh to active / auto-refresh
command period (tRFC)
43 Maximum cycle time (tCK max)
44 Maximum DQS-DQ skew time (tDQSQ)
45 Maximum read data hold skew factor (tQHS)
46~61 Superset Information(may be used in future)
62 SPD Revision code
63 Checksum for Bytes 0~62
HYMD132725B(L)8J-J
Bin Sort : J(DDR333@CL=2.5)
Function Supported
128 Bytes
256 Bytes
DDR SDRAM
12
10
2Bank
72 Bits
-
SSTL 2.5V
6.0ns
+/-0.7ns
ECC
15.6us & Self refresh
x8
x8
Hexa Value
80h
08h
07h
0Ch
0Ah
02h
48h
00h
04h
60h
70h
02h
80h
08h
08h
Note
1
1
2
2
1 CLK
01h
2,4,8
0Eh
4 Banks
04h
2, 2.5
0Ch
0
01h
1
02h
differential clock input
20h
+/-0.2Voltage tolerance,
Concurrent Auto Precharge
C0h
tRAS Lock Out
7.5ns
75h
+/-0.7ns
70h
-
00h
-
00h
18ns
48h
12ns
30h
18ns
48h
42ns
2Ah
128MB
20h
0.75ns
75h
0.75ns
75h
0.45ns
45h
0.45ns
45h
Undefined
00h
60ns
3Ch
72ns
48h
12ns
30h
0.45ns
2Dh
0.55ns
55h
Undefined
00h
Initial release
00h
-
F0h
Rev. 0.3/Jul. 02
15