HY5PS1G831F Datasheet, PDF (14/33 Pages) Hynix Semiconductor – 1Gb DDR2 SDRAM

1HY5PS1G431(L)F
1HY5PS1G831(L)F
Note 5: The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as
measured from AC to AC. This is guaranteed by design and characterization.
Note 6: This represents the step size when the OCD is near 18 ohms at nominal conditions across all process cor-
ners/variations and represents only the DRAM uncertainty. A 0 ohm value(no calibration) can only be achieved if the
OCD impedance is 18 ohms +/- 0.75 ohms under nominal conditions.
Output Slew rate load:
VTT
25 ohms
Output
(Vout)
Reference
point
Note 7: DRAM output slew rate specification applies to 400MT/s & 533MT/s speed bins.
Note 8: Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in
tDQSQ and tQHS specification.
Rev. 1.2 / Dec 2006
14