HYMD512M646AFS8-D43 Datasheet, PDF (11/17 Pages) Hynix Semiconductor – Unbuffered DDR SO-DIMM

HYMD512M646A(L)FS8-D43/D4
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
Symbol
DDR400 (D43)
Min
Max
Input Pulse Width
tIPW
2.2
-
Write DQS High Level Width
tDQSH
0.35
-
Write DQS Low Level Width
tDQSL
0.35
-
Clock to First Rising edge of DQS-In
tDQSS
0.72
1.28
DQS falling edge to CK setup time
tDSS
0.2
DQS falling edge hold time from CK
tDSH
0.2
Data-In Setup Time to DQS-In (DQ & DM)
tDS
0.4
-
Data-in Hold Time to DQS-In (DQ & DM)
tDH
0.4
-
DQ & DM Input Pulse Width
tDIPW
1.75
-
Read DQS Preamble Time
tRPRE
0.9
1.1
Read DQS Postamble Time
tRPST
0.4
0.6
Write DQS Preamble Setup Time
tWPRES
0
-
Write DQS Preamble Hold Time
tWPREH
0.25
-
Write DQS Postamble Time
tWPST
0.4
0.6
Mode Register Set Delay
tMRD
2
-
Exit Self Refresh to Any Execute Command
tXSC
200
-
Average Periodic Refresh Interval
tREFI
-
7.8
DDR400 (D4)
Min
Max
2.2
-
0.35
-
0.35
-
0.72
1.28
0.2
0.2
0.4
-
0.4
-
1.75
-
0.9
1.1
0.4
0.6
0
-
0.25
-
0.4
0.6
2
-
200
-
-
7.8
- continued -
Unit Note
ns
6
CK
CK
CK
CK
CK
ns 6,7,11
,
ns 12,13
ns
6
CK
CK
CK
CK
CK
CK
CK
8
us
Note :
1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3. For command/address input slew rate >=1.0V/ns
4. For command/address input slew rate >=0.5V/ns and <1.0V/ns
This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold
5. Slew-rate Derating Table.
Input Setup / Hold Slew-rate
Delta tIS
Delta tIH
V/ns
ps
ps
0.5
0
0
0.4
+50
0
0.3
+100
0
6. CK, /CK slew rates are >=1.0V/ns
7. These parameters quarantee device timing, but they are not necessarily tested on each device, and they may be quaranteed by
design or tester correlation.
Rev. 0.2 / Apr. 2004
11