HWF1686YC Datasheet, PDF (1/3 Pages) Hexawave, Inc – L-Band Power FET Via Hole Chip

Features
Output Power: P_1dB=30dBm(typ.)
High Gain: G_L=16dB(typ.)
High Efficiency: PAE=45%(typ.)
High Linearity: IP₃=45dBm(typ.)
Description
Designed for various RF and Microwave
applications, the HWF1686YC is a
medium power GaAs MESFET chip with 2
mm gate width and 0.7 µm gate length.
HWF1686YC
L-Band Power FET Via Hole Chip
Autumn 2002 V1
Outline Dimensions
650
μ Unit : m
Thickness: 53±5
All Bond Pads:
60 x 60
435
1
Source
3
Absolute Maximum Ratings
215
2
4
V_DS
V_GS
I_D
I_G
T_CH
T_STG
P_T*
Drain to Source Voltage
Gate to Source Voltage
Drain Current
Gate Current
Channel Temperature
Storage Temperature
Power Dissipation
* mounted on an infinite heat sink
+15V
-5V
I_DSS
2mA
175_°C
-65 to +175_°C
5.4W
Electrical Specifications (TA=25_°C)
Source
0.0
0.0 58.5
344.5 400
Bond Pads:
1 to 2: Gate
3 to 4: Drain
Source electrodes are connected
to the bottom of the chip by
via-holes
Symbol
Parameters
I_DSS
V_P
g_m
R_th
P_1dB
G_L
PAE
IP₃
Saturated Drain Current
Pinch-off Voltage
Transconductance
Thermal Resistance
Output Power @1dB Gain
Linear Power Gain
Power-added Efficiency (P_out = P_1dB)
Third-order Intercept Point^*
Conditions
V_DS=3V, V_GS=0V
V_DS=3V, I_DS=20mA
V_DS=3V, I_DS=200mA
Channel to Case
V_DS=10V
I_DS=0.5I_DSS
f=2.4GHz
Units
mA
V
mS
°^C/W
dBm
dB
%
dBm
Min.
300
-3.5
-
-
29.0
15
-
-
Typ.
400
-2.0
200
20
30.0
16
45
45
Max.
600
-1.5
-
28
-
-
-
-
*: Single carrier level 15dBm, 1 MHz apart between 2 tones, current adjusted for best IP₃
Bonding Manner
Gate, drain, pad: 1 wire on each pad
Source pad: 2 wires on each side
Hexawave Inc. 2 Prosperity Road II, Science Park, Hsinchu, Taiwan, R.O.C.. TEL [phone] FAX [phone]
http://www.hw.com.tw Email: [e-mail] All specifications are subject to change without notice.