HCPL-0370 Datasheet, PDF (9/13 Pages) Agilent(Hewlett-Packard) – AC/DC to Logic Interface Optocouplers

9
Notes:
1. Measured at a point 1.6 mm below seating plane.
2. Current into/out of any single lead.
3. Surge input current duration is 3 ms at 120 Hz pulse repetition rate. Transient input current duration is 10 µs at 120 Hz pulse
repetition rate. Note that maximum input power, P_IN, must be observed.
4. Derate linearly above 70°C free-air temperature at a rate of 4.1 mW/°C (HCPL-3700/3760) and 3.1 mW/°C (HCPL-0370). Maximum
input power dissipation of 230 mW (HCPL-3700/3760) and 172 mW (HCPL-0370) allows an input IC junction temperature of 125°C
at an ambient temperature of T_A = 70°C. Excessive P_IN and T_J may result in IC chip degradation.
5. Derate linearly above 70°C free-air temperature at a rate of 5.4 mW/°C (HCPL-3700/3760) and 5 mW/°C (HCPL-0370).
6. Derate linearly above 70°C free-air temperature at a rate of 3.9 mW/°C (HCPL-3700/3760) and 1.9 mW/°C (HCPL-0370). Maximum
output power dissipation of 210 mW (HCPL-3700/3760) and 103 mW (HCPL-0370) allows an output IC junction temperature of
125°C at an ambient temperature of T_A = 70°C.
7. Derate linearly above 70°C free-air temperature at a rate of 0.6 mA/°C.
8. Maximum operating frequency is defined when output waveform Pin 6 obtains only 90% of V_CC with R_L = 4.7 kΩ, C_L = 30 pF using
a 5 V square wave input signal.
9. All typical values are at T_A = 25°C, V_CC = 5.0 V unless otherwise stated.
10. The t_PHL propagation delay is measured from the 2.5 V level of the leading edge of a 5.0 V input pulse (1 µs rise time) to the 1.5 V
level on the leading edge of the output pulse (see Figure 10).
11. The t_PLH propagation delay is measured from the 2.5 V level of the trailing edge of a 5.0 V input pulse (1 µs fall time) to the 1.5 V
level on the trailing edge of the output pulse (see Figure 10).
12. Common mode transient immunity in Logic High level is the maximum tolerable (positive) dV_CM/dt on the leading edge of the
common mode pulse, V_CM, to insure that the output will remain in a Logic High state (i.e., V_O > 2.0 V). Common mode transient
immunity in Logic Low level is the maximum tolerable (negative) dV_CM/dt on the trailing edge of the common mode pulse signal,
V_CM, to insure that the output will remain in a Logic Low state (i.e., V_O < 0.8 V). See Figure 11.
13. In applications where dV_CM/dt may exceed 50,000 V/µs (such as static discharge), a series resistor, R_CC, should be included to
protect the detector IC from destructively high surge currents. The recommended value for R_CC is 240 Ω per volt of allowable drop
in V_CC (between Pin 8 and V_CC) with a minimum value of 240 Ω.
14. Logic low output level at Pin 6 occurs under the conditions of V_IN ≥ V_TH+ as well as the range of V_IN > V_TH– once V_IN has exceeded
V_TH+. Logic high output level at Pin 6 occurs under the conditions of V_IN ≤ V_TH- as well as the range of V_IN < V_TH+ once V_IN has
decreased below V_TH-.
15. AC voltage is instantaneous voltage.
16. Device considered a two terminal device: Pins 1, 2, 3, 4 connected together, and Pins 5, 6, 7, 8 connected together.
17. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 V rms for 1 second
(leakage detection current limit, I_i-o ≤ 5 µA).
18. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second
(leakage detection current limit, I_i-o ≤ 5 µA). This test is performed before the 100% production test for partial discharge (Method b)
shown in the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table.
INPUT
DEVICE
TH₊
TH_– CONNNECTION
I_TH HCPL-0370/3700 2.5 mA 1.3 mA
HCPL-3760 1.2 mA 0.6 mA
PINS 2, 3
OR 1, 4
V_TH(dc)
V_TH(ac)
ALL
ALL
3.7 V
4.9 V
2.6 V
3.7 V
PINS 2, 3
PINS 1, 4
Figure 1. Typical Input
Characteristics, I_IN vs. V_IN (AC Voltage
is Instantaneous Value).
Figure 2. Typical Transfer Characteristics.