HBCR-1610 Datasheet, PDF (6/10 Pages) Agilent(Hewlett-Packard) – Single Chip Bar Code Decode IC

Surface Mount IC Drying
Whenever Vapor Phase or Infra-
red Reflow technologies are used
to mount either of the surface
mount packages, there is a possi-
bility that previously absorbed
moisture, heated very rapidly to
the reflow temperatures, may
cause the package to crack from
internal stresses. There is a
reliability concern that moisture
may then enter the package over
a period of time, and metal
corrosion may take place,
degrading the IC performance.
To reduce the amount of
absorbed moisture and prevent
cracking, all of the surface mount
ICs should undergo one of the
following baking cycles. The
parts MUST then be mounted
within 48 hours. If the parts are
not mounted within 48 hours,
they must be rebaked.
The total number of baking cycles
must not exceed two (2). If the
ICs are baked more than twice,
Hewlett-Packard cannot guaran-
tee the performance and
reliability of the parts.
Neither bake cycle can be per-
formed in the standard shipping
tubes. The ICs must be baked in
an ESD safe, mechanically stable
container, such as an aluminum
tube or pan.
Cycle
A
B
Temper-
ature
125°C
60°C
Time
24 Hours
96 Hours
Note: Cycle B must be done in an
atmosphere of <5% relative humidity air
or nitrogen.
Stand Alone Decoder
(Parallel Mode)
+5 V
150 Ω
2N5088
47 KΩ
+5 V
10 KΩ
SDI
EX3
C3C
I2C
CST
UEE
UE1
FRQ
CSS
GRB
U5S
U2S
V_CC
EA
RST
BPR
LED
CRD
CDY
DWR
DDY
RTS
WR
RD
PDR
PGB
PP7
PP6
PP5
PP4
PP3
PP2
SDI
PP1
XTAL 1
PP0
XTAL 2
IOM
GND
HBCR-161X
+5 V ^{+5 V}
10 µF
500 Ω
1N4148
10 Ω
10 KΩ
2N2907
0.047 µF
10
mH
+5 V
1N4148
PIEZO
BEEPER
1
23
3
21
CAB
CBA
DIR
G
11
10
9
8
7
6
5
4
A8
A7
A6
A5
A4
A3
A2
A1
V_CC
SBA
SAB
V_SS
24
22
2
12
B8
B7
B6
B5
B4
B3
B2
B1
13
14
15
16
17
18
19
20
CRD
CDY
DWR
DDY
RTS
+5 V
D8
D7
D6
D5
D4
D3
D2
D1
NOTES:
1. USE THE CORRECT CAPACITOR FOR
EITHER A CRYSTAL OR A CERAMIC
RESONATOR. SEE THE USERS MANUAL.
2. SEE PIN DIAGRAMS FOR THE PINOUT
OF THE DECODE IC. PIN NUMBERS VARY
WITH PACKAGE.
3. VOLUME OF THE BEEPER CIRCUIT IS
ADJUSTABLE BY VARYING THE VALUE
OF THE 500 Ω POT.
4. AN ALTERNATIVE CIRCUIT USING TWO
74HCT574 OCTAL LATCHES INSTEAD OF
THE 74HCT646 IS IN THE USERS MANUAL.
5. THE LOGIC LEVELS OF THE SDI SCANNER
INPUT IS AS FOLLOWS: BLACK = HIGH,
WHITE = LOW.
74HCT646
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