HCTL-2032 Datasheet, PDF (5/20 Pages) Agilent(Hewlett-Packard) – Quadrature Decoder/Counter Interface ICs

Functional Pin Description
Table 4. Functional Pin Descriptions.
Pin
Symbol
HCTL
2032/
2032-SC
HCTL
2022
Description
V_DD
1
1
Power Supply
V_SS
18
12
Ground
CLK
5
3
CLK is a Schmitt-trigger input for the external clock signal.
CHA_X
15
CHA_Y
16
CHB_X
14
CHB_Y
13
CHI_X
17
CHI_Y
19
RSTNX 12
RSTNY 11
10
CHA_X, CHA_Y, CHB_X, and CHB_Y are Schmitt-trigger inputs that accept the outputs from
NC
a quadrature-encoded source, such as incremental optical shaft encoder. Two
9
channels, A and B, nominally 90 degrees out of phase, are required. CHA_X and CHB_X
NC
are the 1^st axis and CHA_Y and CHB_Y are the 2^nd axis.
11
CHI_X and CHI_Y are Schmitt-trigger inputs that accept the outputs of Index channel
NC
from an incremental optical shaft encoder.
8
This active low Schmitt-trigger input clears the internal position counter and the
NC
position latch. It also resets the inhibit logic. RST_X/ and RST_Y/ are asynchronous with
respect to any other input signals. RST_X/ is to reset the 1^st axis counter and RST_Y/ is
to reset the 2^nd axis counter.
OEN
7
5
This CMOS active low input enables the tri-state output buffers. The OE/, SEL1, and
SEL2 inputs are sampled by the internal inhibit logic on the falling edge of the clock to
control the loading of the internal position data latch.
SEL1
6
4
These CMOS inputs directly controls which data byte from the position latch is
SEL2
26
17
enabled into the 8-bit tri-state output buffer. As in OE/ above, SEL₁ and SEL₂ also
control the internal inhibit logic.
BYTE SELECTED
SEL1
SEL2
MSB
2ND
3RD
LSB
0
1
D4
1
1
0
0
1
0
D3
D2
D1
EN1
2
EN2
3
NC
These CMOS control pins are set to high or low to activate the selected count mode
NC
before the decoding begins.
X/Y
32
Count Modes
EN1
EN2
4x
2x
1x
0
0
Illegal Mode
1
0
On
0
1
On
1
1
On
NC
Select the 1^st or 2^nd axis data to be read. Low bit enables the 1^st axis data, while high
bit enables the 2^nd axis data.
CNTDEC_X 27
CNTDEC_Y 28
NC
A pulse is presented on this LSTTL-compatible output when the quadrature decoder
NC
(4x/2x/1x) has detected a state transition. CNTDEC_X is for 1^st axis and CNTDEC_Y is
for 2^nd axis.
U/Dx
8
U/Dy
9
6
This LSTTL-compatible output allows the user to determine whether the IC is
NC
counting up or down and is intended to be used with the CNTDEC and CNTCAS
outputs. The proper signal U (high level) or D/ (low level) will be present before the
rising edge of the CNTDEC and CNTCAS outputs.
5