HCTL-2032 Datasheet, PDF(16/20 Page) Agilent(Hewlett-Packard) – Quadrature Decoder/Counter Interface ICs

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HCTL-2032 Datasheet, PDF (16/20 Pages) Agilent(Hewlett-Packard) – Quadrature Decoder/Counter Interface ICs

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Cascade Considerations

(HCTL-2032 / 2032-SC only)

The HCTL- 2032 / 2032- SC 's

cascading system allows for

position reads of more than

four bytes. These reads can be

accomplished by latching all the

bytes and then reading the

bytes sequentially over the 8- bit

bus. It is assumed here that,

externally, a counter followed by

a latch is used to count any

count that exceeds 32 bits. This

configuration is compatible with

the HCTL- 2032 / 2032- SC

internal counter/latch

combination.

Consider the sequence of events

for a read cycle that starts as

the HCTL- 2032 / 2032- SC 's

internal counter rolls over. On

the rising clock edge, count data

is updated in the internal

counter, rolling it over. A count-

cascade pulse (CNTCAS) will be

generated with some delay after

the rising clock edge (tCHD).

There will be additional

propagation delays through the

external counters and registers.

Meanwhile, with SEL and OE

low to start the read, the

internal latches are inhibited at

the falling edge and do not

update again till the inhibit is

reset.

If the CNTCAS pulse now toggles

the external counter and this

count gets latched a major

count error will occur. The

count error is because the

external latches get updated

when the internal latch is

inhibited.

Valid data can be ensured by

latching the external counter

data when the high byte read is

started (SEL and OE low). This

latched external byte

corresponds to the count in the

inhibited internal latch. The

cascade pulse that occurs

during the clock cycle when the

read begins gets counted by the

external counter and is not lost.

For example, suppose the

HCTL- 2032 / 2032- SC count is

at FFFFFFFFh and an external

counter is at F0h, with the

count going up. A count

occurring in the HCTL- 2032 /

2032- SC will cause the counter

to roll over and a cascade pulse

will be generated. A read

starting on this clock cycle will

show FFFFFFFFh from the

HCTL- 2032 / 2032- SC. The

external latch should read F0h,

but if the host latches the count

after the cascade signal

propagates through, the external

latch will read F1h.

CLK

CHA FLT

CHB FLT

U/Dbar

CNT DCDR

CNT cas

COUNT

FFFFFFFDh

FFFFFFFEh

Figure 16. Decode and Cascade Output Diagram (4x)

FFFFFFFh

00000000h

FFFFFFFEh

FFFFFFFh

16

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