HCMS-39X2 Datasheet, PDF (11/22 Pages) Agilent(Hewlett-Packard) – 3.3 V High Performance CMOS 5x7 AlphaNumeric Displays

RS
CE
CLK
D_IN
D_OUT (SERIAL)
D_OUT
(SIMULTANEOUS)
T_RSS T_RSH
1
2
T_CLKCE
3
T _CES
4
T _CLKH
11
T _CEDO
10
T_DS
6
T _DH
7
T_DOUT
8
T _DOUTP
9
T_CLKL
12
T_CEH
5
[1]
NEW DATA LATCHED HERE
LED OUTPUTS,
CONTROL
REGISTERS
PREVIOUS DATA
NOTE:
1. DATA IS COPIED TO THE CONTROL REGISTER OR THE DOT LATCH AND LED OUTPUTS WHEN CE IS HIGH AND CLK IS LOW.
NEW DATA
Figure 5. HCMS-39XX write cycle timing diagram.
Pixel Map
In a 4-character display, the 160-
bits are arranged as 20 columns
by 8 rows. This array can be
conceptualized as four 5 x 8 dot
matrix character locations, but
only 7 of the 8 rows have LEDs
(see Figures 6 & 7). The bottom
row (row 0) is not used. Thus,
latch location 0 is never
displayed. Column 0 controls the
left-most column. Data from Dot
Latch locations 0-7 determine
whether or not pixels in Column
0 are turned-on or turned-off.
Therefore, the lower left pixel is
turned-on when a logic high is
stored in Dot Latch location 1.
Characters are loaded in serially,
with the left-most character
being loaded first and the right-
most character being loaded last.
By loading one character at a
time and latching the data before
loading the next character, the
figures will appear to scroll from
right to left.
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