RGR1551 Datasheet, PDF (1/6 Pages) Agilent(Hewlett-Packard) – Fiber Optic “Light to Logic” Receiver with Clock Recovery

Fiber Optic “Light to Logic”
Receiver with Clock Recovery
Preliminary Technical Data
RGR1551
Features
• Light to Logic 20-Pin DIP
Receiver Offers ECL
Compatibility
• Long Reach, High
Performance
• Sensitivity:
–36 dBm
• Phase-Locked Loop (PLL)
Timing Recovery Circuit
• Meets SONET Jitter
Tolerance Requirements
(CCITT G.958)
• Single +5 V Supply,
Typically <700 mW
• SONET OC3 and SDH STM1
Compatible
• Multisourced
Applications
• Telecommunication
Networks
• SONET OC3 and SDH STM1
Compatible
• Local and Metropolitan Area
Networks
• ATM Single Mode Public
Network
• Military Communications
and Control Systems
• Digital Cable TV Networks
to 1600 nm wavelength light
wave information into an
electrical signal at a data rate of
155 Mb/s.
The receiver contains an InGaAs
PIN photodiode, a high sensitiv-
ity, wide dynamic range transim-
pedance amplifier, capacitively
coupled to a PLL based clock
recovery circuit. The clock and
data outputs are retimed
complementary PECL.
Description
The RGR1551 receiver provides
optical signal conversion and
processing. It converts 1200 nm
A complementary CMOS
compatible low light alarm is also
provided.
Preliminary Product Disclaimer
This preliminary data sheet is provided to assist you in the evaluation of engineering samples of the product which is under development
and targeted for release during 1997. Until Hewlett-Packard releases this product for general sales, HP reserves the right to alter prices,
specifications, features, capabilities, function, manufacturing release dates, and even general availability of the product at any time.
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