RFM42B Datasheet, PDF (30/51 Pages) List of Unclassifed Manufacturers – ISM TRANSMITTER

RFM42B/43B
6. Data Handling and Packet Handler
The internal modem is designed to operate with a packet including a 10101... preamble structure. To configure the
modem to operate with packet formats without a preamble or other legacy packet structures contact customer
support.
6.1. TX FIFO
A 64 byte FIFO is integrated into the chip for TX, as shown in Figure 11. "Register 7Fh. FIFO Access" is used to
access the FIFO. A burst write, as described in "3.1. Serial Peripheral Interface (SPI) " , to address 7Fh
will write data to the TX FIFO.
TX FIFO
TX FIFO Almost Full
Threshold
TX FIFO Almost Empty
Threshold
Figure 11. FIFO Threshold
The TX FIFO has two programmable thresholds. An interrupt event occurs when the data in the TX FIFO reaches
these thresholds. The first threshold is the FIFO almost full threshold, txafthr[5:0]. The value in this register
corresponds to the desired threshold value in number of bytes. When the data being filled into the TX FIFO crosses
this threshold limit, an interrupt to the microcontroller is generated so the chip can enter TX mode to transmit the
contents of the TX FIFO. The second threshold for TX is the FIFO almost empty Threshold, txaethr[5:0]. When the
data being shifted out of the TX FIFO drops below the almost empty threshold an interrupt will be generated. The
microcontroller will need to switch out of TX mode or fill more data into the TX FIFO. The transceiver can be
configured so that when the TX FIFO is empty it will automatically exit the TX state and return to one of the low
power states. When TX is initiated, it will transmit the number of bytes programmed into the packet length field
(Reg 3Eh). When the packet ends, the chip will return to the state specified in register 07h. For example, if 08h is
written to address 07h then the chip will return to the STANDBY state. If 09h is written then the chip will return to
the READY state.
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