HMC6343 Datasheet, PDF (7/13 Pages) Honeywell Solid State Electronics Center – 3-Axis Digital Compass Module

HMC6343
Mounting Orientations
The HMC6343 provides for three standard mounting orientations, with a flat horizontal orientation the factory set default.
For vertical mounting, there are two upright orientations with either the X-axis or the Z-axis designated as the forward
reference directions. To change the forward reference direction, send the appropriate command byte (0x72, 0x73, or
0x74) for level or upright orientations, and reset the processor (or cycle power). To enjoy other orientations, you can add
or subtract 90 degree increments of deviation angle as required from the three choices. The figure below shows pictorially
the orientations.
Y
Z
Y
X
Z
Y
x
Z
X
LEVEL
0x72
UPRIGHT EDGE
0x73
UPRIGHT FRONT
0x74
HMC6343 ORIENTATIONS
Red Arrow is the Forward Direction
I²C COMMUNICATION PROTOCOL
The HMC6343 communicates via a two-wire I²C bus system as a slave device. The HMC6343 uses a layered protocol
with the interface protocol defined by the I²C bus specification, and the lower command protocol defined by Honeywell.
The data rate is the standard-mode 100kbps rate as defined in the I²C Bus Specification 2.1. The bus bit format is an 8-bit
Data/Address send and a 1-bit acknowledge bit. The format of the data bytes (payload) shall be case sensitive ASCII
characters or binary data to the HMC6343 slave, and binary data returned. Negative binary values will be in two’s
complement form. The default (factory) HMC6343 7-bit slave address is 0x32 for write operations, or 0x33 for read
operations.
The HMC6343 Serial Clock (SCL) and Serial Data (SDA) lines do not have internal pull-up resistors, and require resistive
pull-ups (Rp) between the master device (usually a host microprocessor) and the HMC6343. Pull-up resistance values of
about 10k ohms are recommended with a nominal 3.3-volt supply voltage. Other values may be used as defined in the I²C
Bus Specification 2.1.
The SCL and SDA lines in this bus specification can be connected to a host of devices. The bus can be a single master to
multiple slaves, or it can be a multiple master configuration. All data transfers are initiated by the master device which is
responsible for generating the clock signal, and the data transfers are 8 bit long. All devices are addressed by I²C’s
unique 7 bit address. After each 8-bit transfer, the master device generates a 9 ^th clock pulse, and releases the SDA line.
The receiving device (addressed slave) will pull the SDA line low to acknowledge (ACK) the successful transfer or leave
the SDA high to negative acknowledge (NACK).
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